Frequency-doubling delay locked loop
AssigneeMosaid Technologies Incorporated
InventorPaul W. Demone
Life of this patent
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Abstract
A frequency multiplier circuit comprising a delay line receiving at one end thereof a reference clock for generating clock tap outputs from respective ones of a plurality of period matched delay elements; a clock combining circuit responsive to pairs of tap outputs for generating a rising and falling edge of an output clock pulse from respective ones of the pairs whereby the output clock period is less than the input clock period.
Claims8
A delay locked loop for generating an output clock signal in response to a reference input clock signal comprising:
- a) a delay line having a predetermined number of serially coupled delay stages, each of said delay stages providing a delay stage tap output;
- b) a plurality of combining circuit cells, each cell having inputs respectively coupled to ones of a predetermined number of delay stage tap outputs, each of said combining cells providing first and second complementary outputs, said outputs of each cell being separated in time by said predetermined number of delay stages and having a multiplied frequency of said reference input clock signal;
- c) a selector responsive to a selection control signal for selecting an output from one of a pair of complementary outputs of one of said combining cells, to produce said output clock signal;
- d) a phase detector responsive to said output clock signal and said reference input clock signal to control said selector for selecting an optimum complimentary output for synchronizing said reference input clock signal and said output clock signal.
A frequency multiplier circuit for generating an output clock signal in response to a rising edge of a reference input clock signal, said multiplier comprising:
- a delay line for receiving and delaying said reference input clock signal, said delay line having a plurality of serially coupled delay stages each having a delay stage tap output;
- a plurality of combining circuit cells, each cell having inputs respectively coupled to ones of a predetermined number of delay stage tap outputs, each of the combining cells providing first and second complementary outputs, the outputs of each cell being separated in time by said predetermined number of delay stages and having a multiplied frequency of said reference input clock signal;
- a selector coupled to said combining cell outputs for selecting an output from said combining cells outputs for producing said output clock signal;
- wherein said frequency multiplier circuit is a delay locked loop;
- wherein the number of said plurality of combining cells is divisible by 4;
- wherein each of said delay stage outputs coupled to said combining cell inputs is
- separated by at least 90 degrees;
- and,
- wherein said combining cells comprising a flip-flop circuit for producing said combining cell output.
A method for generating an output clock signal in response to a rising edge of a reference input clock signal, said method comprising the steps of:
- a) receiving and delaying said reference input clock signal using a plurality of serially coupled delay stages each having a delay stage tap output;
- b) providing a plurality of output signals, each having a multiplied frequency of said reference input clock signal using a plurality of combining circuit cells, each cell having inputs respectively coupled to ones of a predetermined number of delay stage tap outputs;
- and
- c) selecting an output from said combining cell outputs for producing said output clock signal, wherein said selected combining cell output has a phase closest to said input reference signal's phase.
Dependencies are inferred from the claim text.