Combinational delay circuit for a digital frequency multiplier

Abstract

A combination delay circuit for use in a frequency multiplier comprises a first delay circuit including a plurality of delay lines each having eight segments each effecting a unit delay time td, a latch array having 8 latch elements, one element disposed for each delay line, each receiving an output from a corresponding one of delay segments, and second through eighth delay circuits each having a single delay element effecting the unit delay time. The corresponding between the latch elements and the second through eighth delay circuits is such that delay times in the outputs of the third, fifth, seventh delay circuits are ¼, ½ and ¾, respectively, of the delay times in the output of the eighth delay circuit. The frequency multiplier having the combinational delay circuit multiplies the reference frequency by double, quadruple, and octuple.

Dependencies are inferred from the claim text.