Clock divider for analysis of all clock edges
AssigneeSun Microsystems, Inc.
InventorsGin S. Yee, Drew G. Doblar
Life of this patent
Estimating the term…
Abstract
A method for dividing a high frequency clock signal for analysis of all clock edges has been developed. The method includes receiving a high frequency clock signal and dividing it up into multiple phases that represent respective edges of the clock signal. The initial phases are generated by the divider with each subsequent phase lagging its preceding phase by one clock cycle. Additional subsequent phases are generated by inverting corresponding initial phases.
Claims15
A method for dividing a clock signal into multiple phases, comprising:
- inputting the clock signal to a clock divider segment group, wherein the clock divider segment group comprises at least one clock divider segment;
- generating a first half of the multiple phases with the clock divider segment group;
- generating a second half of the multiple phases with an inverse output from the clock divider segment group;
- and
- aligning the first half and the second half of the multiple phases based on a timing of the clock signal.
A method for dividing a clock signal, comprising:
- inputting the clock signal to a divider;
- generating a first phase of the clock signal with the divider;
- generating a second phase of the clock signal with the divider, wherein the second phase lags behind the first phase by one clock cycle;
- generating a third phase of the clock signal by inverting the first phase;
- generating a fourth phase of the clock signal by inverting the second phase;
- and
- aligning the first phase, the second phase, the third phase, and the fourth phase of the clock signal based on a timing of the clock signal.
An apparatus for dividing a clock signal, comprising:
- a means for inputting the clock signal to a divider;
- means for generating multiple initial phases of the clock signal with the divider;
- means for generating multiple additional phases of the clock signal by inverting the corresponding initial phases of the clock signal;
- and
- means for aligning the multiple initial phases and the multiple additional phases of the clock signal based on a timing of the clock signal.
An apparatus for dividing a clock signal, comprising:
- a divider input that receives the clock signal;
- a first phase generator that couples to the divider input and generates a first phase of the clock signal;
- a second phase generator that couples to the divider input and generates a second phase of the clock signal, wherein the second phase lags behind the first phase by one clock cycle;
- a third phase generator that couples to the first phase and generates a third phase of the clock signal by inverting the first phase;
- a fourth phase generator that couples to the second phase and generates a fourth phase of the clock signal by inverting the second phase;
- and
- an alignment generator that couples to and aligns each of the first phase, the second phase, the third phase, and the fourth phase based on a timing of the clock signal.
Dependencies are inferred from the claim text.