Frequency division/multiplication with jitter minimization
AssigneeBroadcom Corporation
InventorsSiavash Fallahi, Myles Wakayama, Pieter Vorenkamp
Life of this patent
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Abstract
A method and system described for producing frequency multiplication/division by any non-integer output signal frequency relative to a reference signal frequency of a Phase-Lock-Loop (PLL), while simultaneously maintaining low jitter. In one embodiment, the invention increases the number of the available clock phases to M and then shifts the output clock phase by one, every K/M cycle. In one aspect of the present invention, this is accomplished by adding a multiplexer (MUX) to the output of the PLL to implement the phase shifting every K/M cycles. In another aspect, the MUX is placed in the feedback loop of the PLL. In one embodiment, a quantizer is used to drive the MUX.
Claims30
An integrated low jitter frequency multiplication/division electronic circuit for multiplying/dividing frequency of a reference signal, the circuit comprising:
- a phase-lock loop (PLL) that receives the reference signal and outputs M number of clock phases based on the reference signal;
- a signal shifter that receives said M number of clock phases and a count signal and outputs a shifted signal;
- a divider that receives said shifted signal and produces a feedback signal for the PLL;
- and
- a counter that receives said M number of clock phases and outputs said count signal to said signal shifter.
A method for multiplying/dividing frequency of a reference signal, comprising the steps of:
- shifting the reference signal by one phase every K/M cycle so that the reference signal is at least one of decreased by (K+1)/K and increased by K/(K+1) to produce a shifted signal;
- dividing the shifted signal by N to produce a feedback signal;
- extending the period of said reference signal at least to T+T/M for frequency division and to T+T/M for frequency multiplication;
- and
- outputting M number of clock phases from the reference signal using a phase-lock loop (PLL) having feedback.
A frequency divider electronic circuit for dividing frequency of a reference signal by a non-integer number, the circuit comprising:
- a clock generator that receives the reference signal and generates M number of clock phases based on the reference signal;
- a signal shifter that receives said M number of clock phases and a count signal and outputs a shifted signal;
- a divider that receives said shifted signal and produces a feedback signal for the clock generator;
- and
- a counter that receives said M number of clock phases and outputs said count signal to said signal shifter.
Dependencies are inferred from the claim text.