Double data rate dynamic logic
AssigneeIntel Corporation
InventorsSteven K. Hsu, Shih-Lien L. Lu, Ram Krishnamurthy
Life of this patent
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Abstract
A double data rate dynamic logic gate in which an evaluation phase is performed for each phase of a clock signal. In one embodiment, an nMOSFET pull-down logic unit is clocked by two nMOSFETs switched in complementary fashion, and dynamic latches provide the output signals. In another embodiment, two nMOSFET pull-down logic units are employed, each clocked by an nMOSFET in complementary fashion, and a static logic unit provides the output signals.
Claims16
A dynamic logic gate having an evaluation phase, the dynamic logic gate comprising:
- an nMOSFET logic unit;
- a first nMOSFET;
- and
- a second nMOSFET;
- wherein the first and second nMOSFETs are coupled to the nMOSFET logic unit so that the dynamic logic gate enters its evaluation phase only if the first nMOSFET is switched ON or the second nMOSFET is switched ON, and such that the first and second nMOSFETs are coupled to switch ON and OFF in complementary fashion with respect to each other.
A circuit comprising:
- a first stage, the first stage comprising:
- a nMOSFET logic unit;
- a first node;
- a first nMOSFET switched according to a clock signal φ1 so that the first node is pulled LOW only if φ1 is HIGH;
- a second node;
- a second nMOSFET switched according to {overscore (φ)}1, the Boolean complement of the clock signal φ1, so that the second node is pulled LOW only if {overscore (φ)}1 is HIGH;
- a first dynamic latch, having an input port connected to the first node and having an output port, and switched according to a clock signal φ4 and its Boolean complement φ4 to provide an output signal at its output port only if the clock signal φ4 is HIGH;
- and
- a second dynamic latch, having an input port connected to the second node and having an output port, and switched according to the clock signals φ4 and {overscore (φ)}4 to provide an output signal at its output port only if the clock signal {overscore (φ)}4 is HIGH.
A dynamic logic gate having an evaluation phase, the dynamic logic gate comprising:
- a logic unit;
- a first transistor switched according to a first clock signal;
- a second transistor switched ON and OFF in complementary fashion with respect to the first transistor;
- and
- wherein the first and second transistors are coupled to the logic unit so that the dynamic logic gate enters its evaluation phase only if the first transistor is switched ON or the second transistor is switched ON.
A dynamic logic gate having an evaluation phase, the dynamic logic gate comprising:
- a first logic unit;
- a second logic unit;
- a first transistor coupled to the first logic unit so that the dynamic logic gate enters its evaluation phase only if the first transistor is switched ON;
- and
- a second transistor coupled to the second logic unit so that the dynamic logic gate enters its evaluation phase only if the second transistor is switched ON;
- wherein the first and second transistors are switched ON and OFF in complementary fashion with respect to each other.
A dynamic logic gate comprising:
- a first node;
- a first nMOSFET logic unit;
- a first nMOSFET coupled to the first nMOSFET logic unit and the first node to pull the first node LOW only if the first nMOSFET is switched ON;
- a second node;
- a second nMOSFET logic unit;
- and
- a second nMOSFET coupled to the second nMOSFET logic unit and the second node to pull the second node LOW only if the second nMOSFET is switched ON;
- wherein the first and second transistors are coupled to switch ON and OFF in complementary fashion with respect to each other.
Dependencies are inferred from the claim text.