Circuit for inhibiting power consumption in low voltage dynamic logic

A circuit for reducing power consumption in a low voltage dynamic logic, comprising:

• a low voltage dynamic logic provided with first MOS transistor having a first conductive type and a second MOS transistor having a second conductive type different from the first conductive type;
• a first power selection unit that applies one of a first prescribed voltage and a second prescribed voltage to a backgate of the first MOS transistor according to an output signal of the dynamic logic;
• and
• a second power selection unit that applies one of a third prescribed voltage and a fourth prescribed voltage to a back gate of the second MOS transistor according to the output signal of the dynamic logic, wherein the first power selection unit comprises,
• a first transistor that outputs a boosting voltage to the back gate of the first MOS transistor according to the output signal, and
• a second transistor that outputs a power voltage to the back gate of the first MOS transistor according to the output signal.

A circuit that reduces power consumption in a low voltage integrated circuit comprising:

• a low voltage dynamic logic provided with first MOS transistor having a first conductive type and a second MOS transistor having a second conductive type different from the first conductive type;
• a logic gate that logically processes an output signal of the dynamic logic;
• a first PMOS transistor that outputs a boosting voltage to a back gate of the first MOS transistor according to the output signal of the dynamic logic;
• a second PMOS transistor that outputs a first prescribed voltage to the back gate of the first MOS transistor according to an output signal of the logic gate;
• a first NMOS transistor that outputs a substrate voltage to a back gate of the second MOS transistor according to the output signal of the dynamic logic;
• and
• a second NMOS transistor that outputs a second prescribed voltage to the back gate of the second MOS transistor according to the output signal of the logic gate.

A circuit for reducing power consumption in a low voltage dynamic logic, comprising:

• a low voltage dynamic logic provided with first MOS transistor having a first conductive type and a second MOS transistor having a second conductive type different from the first conductive type;
• a first power selection unit that applies one of a first prescribed voltage and a second prescribed voltage to a back gate of the first MOS transistor according to an output signal of the dynamic logic;
• and
• a second power selection unit that applies one of a third prescribed voltage and a fourth prescribed voltage to a back gate of the second MOS transistor according to the output signal of the dynamic logic, wherein the second power selection unit comprises,
• a first transistor that outputs a substrate voltage to the back gate of the second MOS transistor according to the output signal, and
• a second transistor that outputs a ground voltage to the back gate of the second MOS transistor according to the output signal of the dynamic logic.

A circuit for reducing power consumption in a low voltage dynamic logic, comprising:

• a low voltage dynamic logic provided with first MOS transistor having a first conductive type and a second MOS transistor having a second conductive type different from the first conductive type;
• a first power selection unit that applies one of a first prescribed voltage and a second prescribed voltage to a back gate of the first MOS transistor according to an output signal of the dynamic logic;
• and
• a second power selection unit that applies one of a third prescribed voltage and a fourth prescribed voltage to a back gate of the second MOS transistor according to the output signal of the dynamic logic, wherein the dynamic logic further comprises a logic circuit having a plurality of transistors coupled in series between the first and second MOS transistors, wherein the plurality of transistors are coupled to receive a plurality of driving signals.