Structure and method of alternating precharge in dynamic SOI circuits
AssigneeInternational Business Machines Corporation
InventorsGeorge M. Braceras, Patrick R. Hansen
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AssigneeInternational Business Machines Corporation
InventorsGeorge M. Braceras, Patrick R. Hansen
Estimating the term…
A structure and method for reducing bipolar current in of a SOI circuit by alternating precharge low and precharge high methodologies comprises a reset signal source coupled to an inverter and a primary node, further coupled to a first and second PFET device; a clock signal source; coupled to a first NFET device and a third PFET device; a first input signal source coupled to a second NFET device and a fourth PFET device; a first NFET stack node coupled to the third PFET device, the first NFET device, the primary node, and the second NFET device; a second input signal source coupled to a third NFET device; a fifth PFET device coupled to the fourth PFET device; a power supply voltage source coupled to the fifth PFET device; and a second NFET node coupled to the fourth PFET device, the second NFET device, and the third NFET device.
A SOI (silicon-on-insulator) circuit for reducing bipolar current comprising:
A system for reducing bipolar current in a SOI (silicon-on-insulator) logic gate circuit, the system comprising:
A system for reducing bipolar current in a SOI (silicon-on-insulator) logic gate circuit, the system comprising:
Dependencies are inferred from the claim text.