Logic device for outputting a signal within a through rate range

A logic device, comprising:

• a control circuit having
• a pair of first-stage output transistors, which are complementarily operated with each other and are controlled according to an inverted signal which is obtained by inverting an input signal received at an input terminal and has a strong driving performance, for outputting an output signal corresponding to the input signal to an output terminal and charging or discharging an output load;
• and
• a pair of second-stage output transistors, which respectively have a driving performance stronger than that of the first-stage output transistors and are complementarily operated with each other, for performing an operation in parallel to the operation of the first-stage output transistors and correcting a through rate of the output signal output from the first-stage output transistors to the output terminal, wherein one second-stage output transistor, which is to be controlled to a turn-off condition, is controlled according to the input signal and a delayed input signal obtained by delaying the input signal to be immediately turned off by a transistor of a strong driving performance, and the other second-stage output transistor, which is to be controlled to a turn-on condition, is controlled according to the input signal and the delayed input signal to be turned on in a latter period changing to the turn-on condition while successively and smoothly controlling the other second-stage output transistor at first by a transistor of a weak driving performance and controlling the other second-stage output transistor at a turning-on speed at which the through rate is set within a prescribed range,
• wherein the first-stage output transistors are a first-stage output first-conductive-type MOS transistor, which is connected with a terminal of a source voltage, and a first-stage output second-conductive type MOS transistor, which is connected with a terminal of a reference voltage, complementarily operated with each other, the second-stage output transistors are a second-stage output first-conductive-type MOS transistor, which is connected with the terminal of the source voltage, and a second-stage output second-conductive-type MOS transistor, which is connected with the terminal of the reference voltage, complementarily operated with each other, and
• the control circuit comprises
• a first driving cell comprising:
• a first-conductive-type MOS transistor of a strong driving performance for controlling the second-stage output first-conductive-type transistor, which is to be controlled to the turn-off condition, to be immediately turned off according to the delayed input signal;
• and
• a second-conductive-type MOS transistor of a weak driving performance, complementarily operated with the first-conductive-type MOS transistor, for controlling the second-stage-output first-conductive-type transistor, which is to be controlled to turn-on condition, to be successively and smoothly turned on in the later period changing to the turn-on condition at the turning-on speed at which the through rate is set within the prescribed range, and
• a second driving cell comprising:
• a second-conductive type MOS transistor of a strong driving performance for controlling the second-stage output second-conductive-type transistor, which is to be controlled to the turn-off condition, to be immediately turned off according to the delayed input signal;
• and
• a first-conductive-type MOS transistor of a weak driving performance, complementarily operated with the second-conductive-type MOS transistor, for controlling the second-stage-output second-conductive-type transistor, which is to be controlled to turn-on condition, to be successively and smoothly turned on in the later period changing to the turn-on condition at the turning-on speed at which the through rate is set within the prescribed range.