Multiplexers for efficient PLD logic blocks
AssigneeCypress Semiconductor Corporation
InventorsChristopher W. Jones, Rochan Sankar
Life of this patent
Estimating the term…
Abstract
A logic section of a programmable logic device comprising a first circuit and a second circuit. The first circuit may be configured to generate a first output in response to a first input, a second input and a third input. The second circuit may be configured to generate a second output and a third output in response to a fourth input and a fifth input. The second output may be coupled to the second input and the first output may be coupled to the fifth input.
Claims22
A logic section of a programmable logic device comprising:
- a first circuit configured to generate a first output in response to a first input, a second input, and a third input;
- and
- a second circuit configured to generate a second output and a third output in response to a fourth input comprising one or more input terms and a fifth input, wherein (i) said second output is coupled to said second input and (ii) said first output is coupled to said fifth input.
A logic section of a programmable logic device comprising:
- means for generating a first output in response to a first input, a second input, and a third input;
- and
- means for implementing user-defined logic configured to generate (i) said second input in response to a fourth input comprising one or more input terms and (ii) a second output in response to said first output.
A method for reducing an output dimension of a product term array of a programmable logic device comprising the steps of:
- (A) receiving a first input, a second input, and a third input;
- (B) performing a user defined logical operation on said second input;
- (C) generating an output in response to said first input when said third input has a first state;
- and
- (D) generating the output in response to a result of the step (B) when said third input has a second state.
A logic section of a programmable logic device comprising:
- a first circuit configured to generate a first output in response to a first input, a second input, and a third input;
- and
- a second circuit configured to generate a second output and a third output in response to a fourth input and a fifth input, wherein (i) said second output is coupled to said second input, (ii) said first output is coupled to said fifth input and (iii) said second circuit is configured to generate a carry output in response to a carry input.
A logic section of a programmable logic device comprising:
- a first circuit configured to generate a first output in response to a first input, a second input, and a third input;
- and
- an XOR array configured to generate a second output and a third output in response to a fourth input and a fifth input, wherein (i) said second output is coupled to said second input and (ii) said first output is coupled to said fifth input.
Dependencies are inferred from the claim text.