Method for the statistical test of integrated circuits
AssigneeSTMicroelectronics S.r.l.
InventorFabien Roulet
Life of this patent
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Abstract
In a method for testing integrated circuits present on a silicon wafer, a full sequence for the test of an integrated circuit comprises a plurality of elementary tests. The test method comprises preliminary steps consisting of the classification of the elementary test steps into statistically essential test steps and statistically secondary test steps and in defining a limited test sequence that comprises only statistically essential elementary test steps. The integrated circuits are then tested by means of a test loop comprising a first test step consisting of the application, to K integrated circuits, of a full test sequence and a second test step consisting of the application, to N following integrated circuits, of a reduced test sequence.
Claims20
A method for testing integrated circuits present on a wafer, in which a plurality of elementary test steps are classified into statistically essential tests and statistically secondary tests and both a full test sequence for an integrated circuit, which includes both the statistically essential elementary tests and the statistically secondary elementary tests, and a limited test sequence for an integrated circuit, which includes only statistically essential elementary test steps, are defined, wherein the method includes a test loop comprising:
- testing K integrated circuits on the wafer in a first test step by application of the full test sequence to each integrated circuit;
- if a number of integrated circuits failing at least one statistically secondary elementary test during the first test step is smaller than a predetermined number Q1, testing N integrated circuits following the K integrated circuits on the wafer in a next test step by application of the limited test sequence to each integrated circuit;
- and
- if the number of integrated circuits failing at least one statistically secondary elementary test during the first test step is greater than or equal to the predetermined number Q1, testing M integrated circuits following the K integrated circuits on the wafer in the next test step by application of the full test sequence to each integrated circuit.
A method for testing integrated circuits present on a wafer, in which a plurality of elementary test steps are classified into statistically essential tests and statistically secondary tests and both a full test sequence for an integrated circuit, which includes both the statistically essential elementary tests and the statistically secondary elementary tests, and a limited test sequence for an integrated circuit, which includes only statistically essential elementary test steps, are defined, wherein the method includes a first test loop comprising:
- testing K integrated circuits on the wafer in a first test step by application of the full test sequence to each integrated circuit;
- and
- if a number of integrated circuits failing at least one statistically secondary elementary test during the first test step is smaller than a predetermined number Q1, testing N integrated circuits following the K integrated circuits on the wafer in a next test step by application of the limited test sequence to each integrated circuit.
A system for testing integrated circuits comprising:
- a test probe;
- and
- a test station, wherein the test station is programmed to carry out a first test loop on a wafer containing a plurality of integrated circuits, the first test loop including:
- testing K integrated circuits on the wafer in a first test step using a full test sequence including both statistically essential elementary tests and statistically secondary elementary tests, and
- if less than a predetermined number Q1 of integrated circuits fail at least one statistically secondary elementary test during the first test step, testing N integrated circuits following the K integrated circuits on the wafer in a next test step using a limited test sequence including only the statistically essential elementary tests.
Dependencies are inferred from the claim text.