Wire-bonded semiconductor device with improved wire arrangement scheme for minimizing abnormal wire sweep

A wire-bonded semiconductor device, which comprises:

• (a) a substrate having a plurality of bond pads including at least one double-wire bond pad;
• (b) a semiconductor chip mounted on the substrate;
• the semiconductor chip having a plurality of bond pads;
• and
• (c) a set of bonding wires interconnected between the chip-side bond pads and the substrate-side bond pads for electrically coupling the semiconductor chip to the substrate;
• the bonding wire set including:
• (c1) a first wire subset arranged along a first side of the wire-bonded semiconductor device adjoining a first corner, the first wire subset being erected to a first loop height;
• (c2) a second wire subset located in the first corner of the wire-bonded semiconductor device and in immediate adjacency to the first wire subset;
• the second wire subset including a number of bonding wires;
• wherein the one located in immediate adjacency to the first wire subset is erected to the first loop height, with every other one being erected to a second loop height smaller than the first loop height;
• (c3) a third wire subset located along a second side of the wire-bonded semiconductor device adjoining a second corner;
• the third wire subset being erected to the first loop height;
• and
• (c4) a fourth wire subset located in the second corner of the wire-bonded semiconductor device and in immediate adjacency to the third wire subset and erected to the second loop height;
• the second wire subset including at least a pair of bonding wires located in immediate adjacency to the third wire subset and bonded together to the double-wire bond pad on the substrate in an intercrossed manner.