High voltage lateral semiconductor device
AssigneeFuji Electric Co., Ltd.
InventorHitoshi Sumida
Life of this patent
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Abstract
A high voltage lateral semiconductor device is provided in which an n buffer region (14) surrounds an n+ drain region (11), and an n drift region (3) surrounds the n buffer region (14), while a p well region (44) surrounds the n drift region (3). No n+ source region is formed in a circular arc portion (47) of the p well region (44), but an n+ source region (46) is formed in each straight portion (48) of the p well region (44). A p+ contact region (45) surrounds the p well region (44) and the n+ source region (46). A gate oxide film is formed on a part of the n+ source region (46) located close to the n drift region, and on the p well region (44) and the outer peripheral portion of the n drill region (3), and a gate electrode is formed on the gate oxide film.
Claims4
A high voltage lateral semiconductor device, comprising:
- a first semiconductor substrate;
- a first-conductivity-type second semiconductor substrate that is bonded to the first semiconductor substrate with an oxide film interposed therebetween, to provide a bonded substrate structure, said second semiconductor substrate being polished to have a desired thickness;
- a second-conductivity-type well region formed in a selected portion of a surface layer of the second semiconductor substrate;
- a high-impurity-concentration second-conductivity-type contact region formed in a selected portion of a surface layer of the second-conductivity-type well region;
- a first-conductivity-type source region formed in a selected portion of the surface layer of the second-conductivity-type well region, such that the source region overlaps the second-conductivity-type contact region;
- a gate electrode layer formed on a gate insulating film, over a part of the second-conductivity-type well region that is interposed between the first-conductivity-type source region and the second semiconductor substrate;
- a source electrode formed on the second-conductivity-type contact region and the first-conductivity-type source region;
- a high-impurity-concentration first-conductivity-type drain region that is formed in a selected portion of the surface layer of the second semiconductor substrate, apart from the second-conductivity-type well region;
- and
- a drain electrode formed on the first-conductivity-type drain region;
- wherein a surface pattern including the second-conductivity-type well region and the first-conductivity-type drain region is formed in an island-like shape in which one of the well region and the drain region surrounds the other thereof, or in a comb-like shape in which the well region and the drain region surround each other;
- and
- wherein the first-conductivity-type source region is not formed at a location where an edge line of the second-conductivity-type well region is opposed to an edge line of the first-conductivity-type drain region, and the length of the edge line of the second-conductivity-type well region is larger than that of the edge line of the first-conductivity-type drain region.
Dependencies are inferred from the claim text.