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US 6,441,428 B1Granted
One-sided floating-gate memory cell
AssigneeMicron Technology, Inc.
InventorRamin Ghodsi
Life of this patent
Estimating the term…
Abstract
Floating-gate memory cells having a control gate for coupling to a word line, a floating gate, a first source/drain region for coupling to a bit line, and a floating second source/drain region are adapted for use in flash memory devices. Such floating-gate memory cells eliminate the need to provide electrical contact to the second source/drain region, thus simplifying the fabrication process and array architecture. The floating-gate memory cells may be programmed using band-to-band tunneling. The floating-gate memory cells may be read using capacitance sensing or forward current sensing techniques.
Claims39
A floating-gate memory cell, comprising:
- a gate overlying a substrate, wherein the substrate has a first conductivity type;
- a first source/drain region formed in the substrate adjacent to the gate and having a second conductivity type different from the first conductivity type;
- and
- a second source/drain region formed in the substrate adjacent to the gate and having the second conductivity type, wherein the second source/drain region is permanently electrically floating.
1 more element
A floating-gate memory cell, comprising:
- a gate dielectric layer overlying a substrate, wherein the substrate has a first conductivity type;
- a floating gate layer overlying the gate dielectric layer;
- an intergate dielectric layer overlying the floating gate layer;
- a control gate layer overlying the intergate dielectric layer for coupling to a word line;
- a first source/drain region formed in the substrate for coupling to a bit line, wherein the first source/drain region has a second conductivity type opposite the first conductivity type;
- and
- a second source/drain region formed in the substrate and having the second conductivity type, wherein no contact is formed to the second source/drain region.
4 more elements
A floating-gate memory cell, comprising:
- a gate dielectric layer overlying a substrate, wherein the substrate has a first conductivity type;
- a floating gate layer overlying the gate dielectric layer;
- an intergate dielectric layer overlying the floating gate layer;
- a control gate layer overlying the intergate dielectric layer for coupling to a word line;
- a first source/drain region formed in the substrate for coupling to a bit line, wherein the first source/drain region has a second conductivity type opposite the first conductivity type;
- a doped region formed in the substrate below the first source/drain region, wherein the doped region has the second conductivity type and wherein the doped region has a dopant level less than a dopant level of the first source/drain region;
- a second source/drain region formed in the substrate and having the second conductivity type, wherein the second source/drain region is electrically floating;
- and
- a channel region in the substrate extending between the first source/drain region and the second source/drain region, wherein the channel region is laterally offset from the doped region.
6 more elements
A floating-gate memory cell, comprising:
- a gate dielectric layer overlying a substrate, wherein the substrate has a first conductivity type;
- a floating gate layer overlying the gate dielectric layer;
- an intergate dielectric layer overlying the floating gate layer;
- a control gate layer overlying the intergate dielectric layer for coupling to a word line;
- a first source/drain region formed in the substrate for coupling to a bit line, wherein the first source/drain region has a second conductivity type opposite the first conductivity type;
- a doped region formed in the substrate below the first source/drain region, wherein the doped region has the second conductivity type and wherein the doped region has a dopant level less than a dopant level of the first source/drain region;
- a second source/drain region formed in the substrate and having the second conductivity type, wherein the second source/drain region is electrically floating;
- and
- a channel region formed in the substrate between the first source/drain region and the second source/drain region, wherein the channel region has the first conductivity type, wherein the channel region has a dopant level higher than a dopant level of the substrate, and wherein the channel region is laterally offset from the doped region.
6 more elements
A memory array, comprising:
- a plurality of memory cells arranged in rows and columns, each memory cell comprising:
- a gate dielectric layer overlying a substrate, wherein the substrate has a first conductivity type;
- a floating gate layer overlying the gate dielectric layer;
- an intergate dielectric layer overlying the floating gate layer;
- a control gate layer overlying the intergate dielectric layer for coupling to a word line;
- a first source/drain region formed in the substrate for coupling to a bit line, wherein the first source/drain region has a second conductivity type opposite the first conductivity type;
- and
- a second source/drain region formed in the substrate and having the second conductivity type, wherein the second source/drain region is electrically floating;
- wherein a first plurality of memory cells have commonly-coupled electrically-floating second source/drain regions and have their first source/drain regions coupled to a first bit line;
- wherein a second plurality of memory cells have commonly-coupled electrically-floating second source/drain regions and have their first source/drain regions coupled to a second bit line different from the first bit line;
- wherein each of the second source/drain regions of the first plurality of memory cells is electrically isolated from each second source/drain region of the second plurality of memory cells;
- and
- wherein at least one word line is coupled to the control gate of a memory cell of the first plurality of memory cells and a memory cell of the second plurality of memory cells.
10 more elements
A memory array, comprising:
- a plurality of memory cells arranged in rows and columns, each memory cell comprising:
- a gate dielectric layer overlying a substrate, wherein the substrate has a first conductivity type;
- a floating gate layer overlying the gate dielectric layer;
- an intergate dielectric layer overlying the floating gate layer;
- a control gate layer overlying the intergate dielectric layer for coupling to a word line;
- a first source/drain region formed in the substrate for coupling to a bit line, wherein the first source/drain region has a second conductivity type opposite the first conductivity type;
- and
- a second source/drain region formed in the substrate and having the second conductivity type, wherein the second source/drain region is electrically floating;
- wherein a first column of memory cells have commonly-coupled electrically-floating second source/drain regions;
- wherein a second column of memory cells have commonly-coupled electrically-floating second source/drain regions;
- and
- wherein each of the second source/drain regions of the first column of memory cells is electrically isolated from each second source/drain region of the second column of memory cells.
9 more elements
A memory array, comprising:
- a plurality of memory cells arranged in rows and columns, each memory cell comprising:
- a gate dielectric layer overlying a substrate, wherein the substrate has a first conductivity type;
- a floating gate layer overlying the gate dielectric layer;
- an intergate dielectric layer overlying the floating gate layer;
- a control gate layer overlying the intergate dielectric layer for coupling to a word line;
- a first source/drain region formed in the substrate for coupling to a bit line, wherein the first source/drain region has a second conductivity type opposite the first conductivity type;
- and
- a second source/drain region formed in the substrate and having the second conductivity type, wherein no contact is formed to the second source/drain region.
5 more elements
A memory array, comprising:
- a plurality of memory cells arranged in rows and columns, each memory cell comprising:
- a gate dielectric layer overlying a substrate, wherein the substrate has a first conductivity type;
- a floating gate layer overlying the gate dielectric layer;
- an intergate dielectric layer overlying the floating gate layer;
- a control gate layer overlying the intergate dielectric layer for coupling to a word line;
- a first source/drain region formed in the substrate for coupling to a bit line, wherein the first source/drain region has a second conductivity type opposite the first conductivity type;
- a second source/drain region formed in the substrate and having the second conductivity type, wherein the second source/drain region is electrically floating;
- a channel region formed in the substrate and having the first conductivity type;
- and
- a doped region formed in the substrate below the first source/drain region and laterally offset from the channel region, wherein the doped region has the second conductivity type and wherein the doped region has a dopant level less than a dopant level of the first source/drain region.
7 more elements
An electronic system, comprising:
- a processor;
- and
- a memory array coupled to the processor, wherein the memory array comprises:
- a plurality of memory cells arranged in rows and columns, each memory cell comprising:
- a gate dielectric layer overlying a substrate, wherein the substrate has a first conductivity type;
- a floating gate layer overlying the gate dielectric layer;
- an intergate dielectric layer overlying the floating gate layer;
- a control gate layer overlying the intergate dielectric layer for coupling to a word line;
- a first source/drain region formed in the substrate for coupling to a bit line, wherein the first source/drain region has a second conductivity type opposite the first conductivity type;
- and
- a second source/drain region formed in the substrate and having the second conductivity type, wherein the second source/drain region is electrically floating;
- wherein a first column of memory cells have commonly-coupled electrically-floating second source/drain regions;
- wherein a second column of memory cells have commonly-coupled electrically-floating second source/drain regions;
- and
- wherein each of the second source/drain regions of the first column of memory cells is electrically isolated from each second source/drain region of the second column of memory cells.
12 more elements
An electronic system, comprising:
- a processor;
- and
- a memory array coupled to the processor, wherein the memory array comprises:
- a plurality of memory cells arranged in rows and columns, each memory cell comprising:
- a gate dielectric layer overlying a substrate, wherein the substrate has a first conductivity type;
- a floating gate layer overlying the gate dielectric layer;
- an intergate dielectric layer overlying the floating gate layer;
- a control gate layer overlying the intergate dielectric layer for coupling to a word line;
- a first source/drain region formed in the substrate for coupling to a bit line, wherein the first source/drain region has a second conductivity type opposite the first conductivity type;
- and
- a second source/drain region formed in the substrate and having the second conductivity type, wherein no contact is formed to the second source/drain region.
8 more elements
An electronic system, comprising:
- a processor;
- and
- a memory array coupled to the processor, wherein the memory array comprises:
- a plurality of memory cells arranged in rows and columns, each memory cell comprising:
- a gate dielectric layer overlying a substrate, wherein the substrate has a first conductivity type;
- a floating gate layer overlying the gate dielectric layer;
- an intergate dielectric layer overlying the floating gate layer;
- a control gate layer overlying the intergate dielectric layer for coupling to a word line;
- a first source/drain region formed in the substrate for coupling to a bit line, wherein the first source/drain region has a second conductivity type opposite the first conductivity type;
- a second source/drain region formed in the substrate and having the second conductivity type, wherein the second source/drain region is electrically floating;
- a channel region formed in the substrate and having the first conductivity type;
- and
- a doped region formed in the substrate below the first source/drain region and laterally offset from the channel region, wherein the doped region has the second conductivity type and wherein the doped region has a dopant level less than a dopant level of the first source/drain region.
10 more elements
A floating-gate memory cell, comprising:
- a gate overlying and in contact with a substrate, wherein the substrate has a first conductivity type;
- a first source/drain region formed in the substrate and adjacent to the gate, wherein the first source/drain region has a second conductivity type opposite the first conductivity type;
- and
- a second source/drain region formed in the substrate and adjacent to the gate, wherein the second source/drain region has the second conductivity type and wherein no contact is formed to the second source/drain region.
1 more element
A floating-gate memory cell, comprising:
- a gate overlying a substrate, wherein the substrate has a first conductivity type;
- a first source/drain region formed in the substrate, wherein the first source/drain region has a second conductivity type opposite the first conductivity type and wherein the first source/drain region coincides with or underlaps the gate;
- a doped region formed in the substrate below the first source/drain region, wherein the doped region has the second conductivity type and wherein the doped region has a dopant level less than a dopant level of the first source/drain region;
- a second source/drain region formed in the substrate and having the second conductivity type, wherein the second source/drain region is electrically floating and wherein the second source/drain region coincides with or underlaps the gate;
- and
- a channel region formed in the substrate extending between the first source/drain region and the second source/drain region, wherein the channel region is laterally offset from the doped region.
3 more elements
A floating-gate memory cell, comprising:
- a gate overlying a substrate, wherein the substrate has a first conductivity type;
- a first source/drain region formed in the substrate, wherein the first source/drain region has a second conductivity type opposite the first conductivity type;
- a doped region formed in the substrate below the first source/drain region, wherein the doped region has the second conductivity type and wherein the doped region has a dopant level less than a dopant level of the first source/drain region;
- a second source/drain region formed in the substrate and having the second conductivity type, wherein the second source/drain region is electrically floating;
- and
- a channel region formed in the substrate between the first source/drain region and the second source/drain region, wherein the channel region has the first conductivity type, wherein the channel region has a dopant level higher than a dopant level of the substrate, and wherein the channel region is laterally offset from the doped region.
3 more elements
Dependencies are inferred from the claim text.