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US 6,441,421 B1Granted
High dielectric constant materials forming components of DRAM storage cells
AssigneeInternational Business Machines Corporation
InventorsLawrence A. Clevenger, Louis L. Hsu, Carl J. Radens, Joseph F. Shepard, Jr.
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Abstract
A method and structure for simultaneously producing a dynamic random access memory device and associated transistor is disclosed. The method forms channel regions and capacitor openings in a substrate. Next, the invention deposits capacitor conductors in the capacitor openings. Then, the invention simultaneously forms a single insulator layer above the channel region and above the capacitor conductor. This single insulator layer comprises a capacitor node dielectric above the capacitor conductor and comprises a gate dielectric above the channel region.
Claims22
A dynamic random access memory device comprising:
- a substrate;
- at least one channel region in said substrate;
- at least one capacitor conductor in said substrate;
- a single planar insulator layer above said channel region and above said capacitor conductor, wherein said single planar insulator layer comprises an upper capacitor node dielectric above said capacitor conductor and comprises a gate dielectric above said channel region;
- and
- a lower capacitor node dielectric below said capacitor conductor.
3 more elements
A dynamic random access memory device comprising:
- a substrate;
- at least one channel region in said substrate;
- at least one capacitor conductor in said substrate;
- a single planar insulator layer above said channel region and above said capacitor conductor, wherein said single planar insulator layer comprises an upper capacitor node dielectric above said capacitor conductor and comprises a gate dielectric above said channel region;
- a lower capacitor node dielectric below said capacitor conductor;
- a single conductor layer above said single planar insulator layer, wherein said single conductor layer comprises a gate conductor above said gate dielectric and a ground plate above said upper capacitor node dielectric;
- spacers on said gate conductor and said ground plate;
- source and drain regions within said substrate, wherein said drain region is in contact with said capacitor conductor and said source region is positioned on an opposite side of said gate conductor from said drain region;
- a covering insulator above said single conductor layer;
- and
- conductive contacts extending through said covering insulator to said source region.
8 more elements
A dynamic random access memory device comprising:
- a substrate;
- at least one channel region in said substrate;
- at least one capacitor conductor in said substrate;
- a single insulator layer above said channel region and above said capacitor conductor, wherein said single insulator layer comprises a capacitor node dielectric above said capacitor conductor and comprises a gate dielectric above said channel region;
- a single conductor layer above said single insulator layer, wherein said single conductor layer comprises a gate conductor above said gate dielectric and a ground plate above said capacitor node dielectric;
- spacers on said gate conductor and said ground plate;
- source and drain regions within said substrate, wherein said drain region is in contact with said capacitor conductor and said source region is positioned on an opposite side of said gate conductor from said drain region;
- a covering insulator above said single conductor layer;
- and
- conductive contacts extending through said covering insulator to said source region,
- wherein said insulating substrate includes shallow trench isolation regions below said capacitor conductors.
8 more elements
A method of producing a dynamic random access memory device, said method comprising:
- forming a capacitor opening in a substrate;
- forming a lower capacitor node dielectric in said capacitor opening;
- forming a capacitor conductor in said capacitor opening;
- simultaneously forming a single planar insulator layer above a channel region of said substrate and above said capacitor conductor, wherein said single planar insulator layer comprises an upper capacitor node dielectric above said capacitor conductor and comprises a gate dielectric above said channel region.
1 more element
A method of simultaneously producing a dynamic random access memory device and associated transistor, said method comprising:
- providing a substrate;
- forming a channel region in said substrate;
- forming a capacitor opening in said substrate;
- forming a lower capacitor node dielectric in said capacitor opening;
- forming a capacitor conductor in said capacitor opening;
- a simultaneously forming a single planar insulator layer above said channel region and above said capacitor conductor, wherein said single planar insulator layer comprises an upper capacitor node dielectric above said capacitor conductor and comprises a gate dielectric above said channel region;
- simultaneously patterning a single conductor layer above said single planar insulator layer, wherein said single conductor layer comprises a gate conductor above said gate dielectric and a ground plate above said upper capacitor node dielectric;
- forming spacers on said gate conductor and said ground plate;
- doping portions of said channel region to form source and drain regions, wherein said drain region is in contact with said capacitor conductor;
- forming a covering insulator above said single conductor layer;
- and
- forming conductive contacts through said covering insulator to said source region.
9 more elements
A method of simultaneously producing a dynamic random access memory device and associated transistor, said method comprising;
- providing a substrate;
- forming a channel region in said substrate;
- forming a capacitor opening in said substrate;
- forming a capacitor conductor in said capacitor opening;
- simultaneously forming a single insulator layer above said channel region and above said capacitor conductor, wherein said single insulator layer comprises a capacitor node dielectric above said capacitor conductor and comprises a gate dielectric above said channel region;
- simultaneously patterning a single conductor layer above said single insulator layer, wherein said single conductor layer comprises a gate conductor above said gate dielectric and a ground plate above said capacitor node dielectric;
- for spacers on said gate conductor and said ground plate;
- doping portions of said channel region to form source and drain regions, wherein said drain region is in contact with said capacitor conductor;
- forming a covering insulator above said single conductor layer;
- and
- forming conductive contacts through said covering insulator to said source region,
- wherein said insulating substrate includes shallow trench isolation regions below said capacitor conductors.
9 more elements
Dependencies are inferred from the claim text.