US 6,441,418 B1 · Spacer narrowed, dual width contact for charge gain reduction

Abstract

A method of forming a contact in an integrated circuit is disclosed herein. The method includes providing a first insulating layer over a semiconductor substrate including first and second gate structures, providing an etch stop layer over the first insulating layer, providing a second insulating layer over the etch stop layer, creating a first aperture in the second insulating layer between the first and second gate structures, forming spacers along the side walls of the first aperture, creating a second aperture in the first insulating layer below the first aperture, and filling the aperture with a conductive material to form the contact. The first aperture has a first aperture width and extends to the etch stop layer. The second aperture has a second aperture width which is less than the first aperture width.

Claims20

Dependent claims

An integrated circuit comprising:

two flash memory gate structures separated by an insulating layer, the insulating layer including an aperture extending from the top of the insulating layer to the bottom of the insulating layer, wherein the aperture defines a contact hole;
an etch stop layer, the etch stop layer being located in the insulating layer;
a conductive contact, the conductive contact being located in the aperture and having a top portion extending from the top of the aperture to the etch stop layer and a bottom portion extending from the top portion to the bottom of the aperture, wherein the entire bottom portion has a width less than the top portion;
and
dielectric spacers, the dielectric spacers being located along side walls of the entire top portion.

2 more elements

Dependencies are inferred from the claim text.

Spacer narrowed, dual width contact for charge gain reduction

Life of this patent

Spacer narrowed, dual width contact for charge gain reduction

Life of this patent

Abstract

Claims20