US 6,441,314 B2Granted

Multilayered substrate for semiconductor device

AssigneeShinko Electric Industries Co., Ltd.

InventorsAkio Rokugawa, Masayuki Sasaki, Yuichi Matsuda

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Abstract

A substrate of multilayered structure having a plurality of sets of an insulation layer and a wiring line layer, and having one face for mounting a semiconductor element thereon and the other face on which external connection terminals are to be provided, the face for mounting a semiconductor element being provided with pads to be bonded to an electrode terminal of the semiconductor element, the other face being provided with pads to be bonded to an external connection terminal, such as a terminal formed of a solder ball, and the wiring line layers on both sides of an insulation layer being connected with each other by vias piercing the insulation layer, wherein the surfaces of the pads to be bonded to an electrode terminal of a semiconductor element are flat and are in the same plane. A method of manufacturing such a multilayered substrate is also disclosed.

Claims13

Dependent claims

A substrate of multilayered structure having a plurality of sets of an insulation layer and a patterned wiring line layer, the substrate having one face for mounting a semiconductor element thereon, the face being provided with pads to be bonded to an electrode terminal of the semiconductor element, and the other face provided with pads to be bonded to an external connection terminal, and each insulation layer having vias piercing therethrough so as to connect a patterned wiring line of the wiring line layer on one side of the insulation layer with a patterned wiring line of the wiring line layer, a pad to be bonded to the electrode terminal of the semiconductor element, or a pad to be bonded to the external connection terminal on the other side of the insulation layer, wherein:

the wiring line layers and the insulation layers are alternately laminated from the face for mounting a semiconductor element to the face provided with pads to be bonded to an external connection terminal,
the surfaces of the pads to be bonded to an electrode terminal of the semiconductor element are in a first plane which is common to the pad surfaces and the surface of the insulation layer, and
each via has a bottom and an opening, the bottom being formed from either the pad to be bonded to an electrode terminal of the semiconductor element or the patterned wiring line of the wiring line layer located at one side of the insulation layer through which the via pierces, the side being closer to the pad to be bonded to an electrode terminal of the semiconductor element, and the opening being located at the other side of the insulation layer through which the via pierces, and the via being connected, at the side of the opening, to either a patterned wiring line of the wiring line layer at the other side of the insulation layer or a pad to be bonded to the external connection terminal.

A multilayered structure having a plurality of sets of an insulation layer and a patterned wiring line layer, the substrate having one face for mounting a semiconductor element thereon, the face being provided with pads to be bonded to an electrode terminal of the semiconductor element, and the other face provided with pads to be bonded to an external connection terminal, and each insulation layer has a plurality of vias piercing therethrough so as to connect a patterned wiring line of the wiring line layer on one side of the insulation layer with a patterned wiring line of the wiring line layer, a pad to be bonded to the electrode terminal of the semiconductor element, or a pad to be bonded to the external connection terminal on the other side of the insulation layer, wherein:

each via has a bottom and an opening;
the wiring line layers and the insulation layers are alternately laminated from the face for mounting a semiconductor element to the face provided with pads to be bonded to an external connection terminal such that a plurality of vias through this insulation layer closest to the face for mounting the semiconductor element each has as a bottom a pad to be bonded to the electrode terminal of the semiconductor element;
the bottom of vias in layers other than those through the insulation layer closest to the face for mounting the semiconductor element being formed from the patterned wiring line of the wiring line layer located at one side of the insulation layer through which the via pierces, the bottom being closer to the pad to be bonded to an electrode terminal of the semiconductor element, and the opening being located at the other side of the insulation layer through which the via pierces, and the via being connected to either a patterned wiring line of the wiring line layer at the other side of the insulation layer or a pad to be bonded to the external connection terminal;
and
a frame member disposed on the in the peripheral region of the face provided with pads to be bonded to an electrode terminal of the semiconductor element.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 09/815,047Filed 23 Mar 2001 · division
Priority: JP 11-6424811 Mar 1999
Published: US 2001/0013425 A116 Aug 2001
Granted: 27 Aug 2002
Term ends: Not estimatedThe source records don’t support an estimate.

Classification28 codes

H05K 3/4682
By building the multilayer layer by layer, i.e. build-up multilayer circuits: manufacture of core-less build-up multilayer circuits on a temporary…
H05K 1/113
Directly combined with via connections: via provided in pad; Pad over filled via
H10P 72/74
For supporting or gripping: using temporarily an auxiliary support
H10W 70/685
Shapes or dispositions thereof: comprising multiple insulating layers