Interconnection of a semiconductor device and a method of forming thereof
AssigneeHynix Semiconductor Inc.
InventorJeong-Eui Hong
Life of this patent
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Abstract
A method for forming an interconnection of a semiconductor device including a step of sequentially stacking a first insulation layer, a first semiconductor layer, a barrier metal layer and a second semiconductor layer on a semiconductor substrate, a step of forming an amorphous first tungsten silicide layer on the second semiconductor layer, a step of transforming the first tungsten silicide layer into a second tungsten silicide layer having a tetragonal crystal structure by an annealing process; a step of forming an etching mask on the second tungsten silicide layer, and a step of sequentially selectively etching the second tungsten silicide layer, the second semiconductor layer, the barrier metal layer and the first semiconductor layer by employing the etching mask.
Claims27
A method for forming an interconnection of a semiconductor device, comprising:
- forming a first insulation layer over a semiconductor substrate;
- forming a first semiconductor layer over the first insulation layer;
- forming a barrier metal layer over the first semiconductor layer;
- forming a second semiconductor layer over the barrier metal layer;
- forming an amorphous first tungsten silicide layer over the second semiconductor layer;
- annealing the amorphous first tungsten silicide layer to form a second tungsten silicide layer having a tetragonal crystal structure;
- forming an etching mask over the second tungsten silicide layer in order to define the interconnection;
- and
- etching the second tungsten silicide layer, the second semiconductor layer, the barrier metal layer and the first semiconductor layer sequentially and preferentially by employing the etching mask.
A method for forming an interconnection of a semiconductor device, comprising:
- providing a semiconductor substrate having an impurity region at its surface;
- forming an insulation layer having a contact hole over the impurity region;
- forming a first semiconductor layer at inner walls and a bottom surface of the contact hole and over the insulation layer;
- forming a barrier metal layer over the first semiconductor layer;
- forming a second semiconductor layer over the barrier metal layer;
- forming an amorphous first tungsten silicide layer over the second semiconductor layer;
- annealing the amorphous first tungsten silicide layer to form a second tungsten silicide layer having a tetragonal crystal structure;
- and
- etching back the second tungsten silicide layer, the second semiconductor layer, the barrier metal layer and the first semiconductor layer sequentially and selectively so that an upper portion of the insulation layer can be exposed.
Dependencies are inferred from the claim text.