Method of copper-polysilicon gate formation
AssigneeAdvanced Micro Devices, Inc.
InventorSergey Lopatin
Life of this patent
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Abstract
In one embodiment, a method for manufacturing a field effect transistor (100) includes forming a polysilicon gate (104) on a surface (106) of a semiconductor substrate (102) in association with adjacent source/drain regions (110, 112) and forming dielectric spacers (124, 126) on sides of the polysilicon gate. The method further includes forming a trench (202) between the dielectric spacers on a surface (200) of the polysilicon gate and filling at least a portion of the trench with barrier and copper or other high conductivity metal to form a copper-polysilicon gate of the field effect transistor.
Claims14
A method of manufacturing a field effect transistor, the method comprising:
- forming a polysilicon gate on a semiconductor substrate in association with adjacent source/drain regions;
- forming dielectric spacers on sides of the polysilicon gate;
- forming a trench between the dielectric spacers on a surface of the polysilicon gate;
- filling at least a portion of the trench with copper to form a copper-polysilicon gate of the field effect transistor;
- depositing a dielectric layer over the copper-polysilicon gate, dielectric spacers and source/drain regions associated with the semiconductor substrate;
- planarizing a top surface portion of the field effect transistor, wherein planarizing comprises removing a portion of the dielectric layer to a predetermined depth related to a thickness of the dielectric spacers;
- selectively depositing electroless metal on the copper-polysilicon gate;
- removing selected portions of the dielectric layer to expose the adjacent source/drain regions and the electroless metal on the copper-polysilicon gate;
- and
- forming a nickel silicide on the adjacent source/drain regions.
A semiconductor manufacturing process comprising the acts of:
- forming a polysilicon gate on a semiconductor substrate;
- forming dielectric spacers on opposing sides of the polysilicon gate;
- etching a predetermined thickness from a surface of the polysilicon gate to define a trench between the dielectric spacers;
- depositing a barrier metal on the surface of the polysilicon gate;
- forming a copper gate on the barrier metal;
- selectively depositing an electroless barrier metal on the copper gate;
- depositing a film of nickel on the semiconductor substrate including on exposed source/drain regions formed adjacent the polysilicon gate;
- and
- forming nickel silicide on the source/drain regions.
Dependencies are inferred from the claim text.