Process of fabricating semiconductor device having low-resistive contact without high temperature heat treatment

A process of fabricating a semiconductor device on a substrate, comprising the steps of

• a) preparing a crystalline silicon layer including a first region having a first conductivity type and a second region spaced apart from said first region and having a second conductivity type opposite to said first conductivity type;
• b) forming an insulating layer over said crystalline silicon layer;
• c) forming a first opening and a second opening in said insulating layer so as to expose said first region and said second region through said first opening and said second opening, respectively;
• d) implanting a first dopant impurity of said first conductivity type into said first region;
• e) implanting a second dopant impurity of said second conductivity type into said second region;
• f) treating said first and second regions with heat under conditions where said first dopant impurity and said second dopant impurity are substantially completely activated;
• g) implanting boron difluoride as a third dopant impurity into said first and second regions in a quantity less than said first dopant impurity and said second dopant impurity so as to make said first and second regions amorphous;
• h) depositing a refractory metal layer on the amorphous first region and the amorphous second region so that said refractory metal layer is in contact with said amorphous first region and said amorphous second region;
• and
• i) treating said refractory metal layer with heat so as to partially convert said refractory metal layer into refractory metal silicide layers in contact with said amorphous first and amorphous second regions.

A process of fabricating a semiconductor device on a substrate, comprising the steps of

• a) preparing a crystalline silicon layer including a first region having a first conductivity type and a second region spaced apart from said first region and having a second conductivity type opposite through said first conductivity type;
• b) forming an insulating layer over said crystalline silicon layer;
• c) forming a first opening and a second opening in said insulating layer so as to expose said first region and said second region to said first opening and said second opening, respectively;
• d) implanting a first dopant impurity of said first conductivity type into said first region;
• e) implanting a second dopant impurity of said second conductivity type into said second region;
• f) treating said first and second regions with heat under conditions where said first dopant impurity and said second dopant impurity are substantially completely activated;
• g) implanting a third dopant impurity into said first and second regions in a quantity less than said first dopant impurity and said second dopant impurity so as to make said first and second regions amorphous;
• h) depositing a refractory metal layer on the amorphous first region and the amorphous second region so that said refractory metal layer is in contact with said amorphous first region and said amorphous second region;
• and
• i) treating said refractory metal layer with heat so as to partially convert said refractory metal layer into refractory metal silicide layers in contact with said amorphous first and amorphous second regions,
• in wich said steps g) includes the sub-steps of:
• g-1) implanting a first sub-dopant impurity of said third dopant impurity of one of said first and second conductivity types into said region through said first opening, and
• g-2) implanting a second sub-dopant impurity of said third dopant impurity of the other of said first and second conductivity types into said second region through said second opening.