Vertical MOSFET

A method of forming a semiconductor memory cell array structure comprising:

• providing a vertical MOSFET DRAM cell structure having a deposited gate conductor layer planarized to a top surface of a trench top oxide on the overlying silicon substrate;
• forming a recess in the gate conductor layer below the top surface of the silicon substrate;
• implanting N-type dopant species through the recess at an angle to form doping pockets in the array P-well;
• depositing an oxide layer into the recess and etching said oxide layer to form spacers on sidewalls of the recess;
• depositing a gate conductor material into said recess and planarizing said gate conductor to said top surface of the trench top oxide.

A method of forming a semiconductor memory cell array structure comprising:

• providing a vertical MOSFET DRAM cell structure having a deposited gate conductor layer planarized to a top surface of a trench top oxide on the overlying silicon substrate;
• forming a recess in the gate conductor layer below the top surface of the silicon substrate;
• depositing an N-doped glass layer into said recess and etching said glass layer to form spacers or sidewalls of the recess;
• depositing a gate conductor material into said recess and planarizing said gate conductor to said top surface of the trench top oxide.