Photoresist spacer process simplification to eliminate the standard polysilicon or oxide spacer process for flash memory circuits

A method of manufacturing flash technology semiconductor devices that eliminates a standard oxide spacer process during the manufacturing process, the method comprising:

• (a) forming gate structures on a semiconductor substrate in regions in which core transistors, n-channel and p-channel transistors will be formed;
• (b) forming PLdd implant regions in regions in which p-channel transistors will be formed;
• (c) forming Nldd implant regions in regions in which n-channel transistors will be formed;
• (d) without forming silicon oxide sidewall spacers on any of the gate structures, forming a first layer of photoresist on exposed surfaces of the gate structures and the semiconductor substrate;
• (e) patterning and developing the first layer of photoresist exposing portions of the n-channel regions in the semiconductor substrate;
• (f) implanting the exposed portions of the n-channel regions with an N+ implant;
• (g) removing the first layer of photoresist;
• (h) forming a second layer of photoresist on exposed surfaces of the gate structures and the semiconductor substrate;
• (i) patterning and developing the second layer of photoresist exposing portions of the p-channel regions in the semiconductor substrate;
• and
• (j) implanting the exposed portions of the p-channel regions with a P+ implant.