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US 6,438,570 B1Granted
FPGA implemented bit-serial multiplier and infinite impulse response
AssigneeXilinx, Inc.
InventorAndrew J. Miller
Life of this patent
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Abstract
A bit-serial multiplier and an infinite impulse response filter implemented therewith, both implemented on an FPGA, are described in various embodiments. The bit-serial multiplier includes function generators configured as a multiplicand memory, a multiplier memory, a product memory, a bit-serial multiplier, and a bit-serial adder. The function generators are arranged to perform bit-serial multiplication of values in the multiplier and multiplicand memories.
Claims15
A bit-serial multiplier implemented on an FPGA, comprising:
- a function generator configured as a multiplicand memory and having address inputs and a data output;
- a function generator configured as a multiplier memory and having address inputs and a data output;
- one or more function generators configured as a product memory, the product memory having address and data inputs and a data output;
- a 2's complement 1×1 bit multiplier implemented with at least two function generators and having inputs coupled to data outputs of the multiplicand and multiplier memories;
- a 1×1 bit adder implemented with at least two function generators and having a first input coupled to the output of the bit-serial multiplier, a second input coupled to the data output of the product memory, and an output coupled to the data input of the product memory;
- and
- a control circuit arranged to address the multiplicand, multiplier, and product memories.
4 more elements
Dependencies are inferred from the claim text.