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US 6,438,178 B1Granted
Integrated circuit for receiving a data stream
AssigneeIntel Corporation
InventorsHenning Lysdal, Michael Liere, Henrik Ingvar Johansen
Life of this patent
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Abstract
An integrated circuit for receiving and recovering an incoming electrical signal of a digital data bit stream transmitted over a communication channel, and comprising an equaliser circuit adapted to reshape the electrical signal to be provided to, a CDR circuit adapted to receive the reshaped electrical signal and to recover data bit signal of the digital bit stream and to recover a clock signal encoded or embedded in the digital data stream.
Claims35
An integrated circuit for receiving and recovering an incoming electrical signal of a digital data bit stream transmitted over a communication channel, and comprising
- an equaliser circuit adapted to reshape the electrical signal to be provided to,
- a CDR circuit adapted to receive the reshaped electrical signal and to recover data bit signal of the digital data bit stream and to recover a clock signal encoded or embedded in the digital data stream, and
- a Loss of Signal (LOS) detection circuit adapted to monitor levels of the incoming electrical signal and further adapted to control a state of a LOS defect signal indicating absence or presence of the digital data bit stream, wherein the LOS detection circuit comprises:
- comparator means adapted to compare voltage levels of the incoming electrical signal to an upper threshold voltage and to provide a first comparator signal indicating whether the incoming voltage levels are larger or smaller than the upper threshold voltage, and adapted to compare the voltage levels of the incoming electrical signal to a lower threshold voltage and to provide a second comparator signal indicating whether the input voltage levels are larger or smaller than the lower threshold voltage,
- detector means adapted to receive and process the first comparator signal and the second comparator signal and to generate a detector output signal having a first level when the incoming signal level is larger than the upper threshold voltage or smaller than the lower threshold voltage and having second logic level when the input signal is between the upper and the lower threshold voltages,
- a controller adapted to receive the recovered clock signal or the recovered data bit signal from the CDR circuit to determine data bit periods of the incoming digital data stream, and adapted to, within each data bit period, detect the presence or absence of the first logic level in the detector output signal, and adapted to control the state of the LOS defect signal indicating absence or presence of the digital data stream based on detected first logic levels and predetermined criteria.
3 more elements
A Loss of Signal (LOS) detection circuit for receiving an incoming electrical signal of a digital data bit stream, and comprising:
- comparator means adapted to compare voltage levels of the incoming electrical signal to an upper threshold voltage and to provide a first comparator signal indicating whether the incoming voltage levels are larger or smaller than the upper threshold voltage, and adapted to compare the voltage levels of the incoming electrical signal to a lower threshold voltage and to provide a second comparator signal indicating whether the input voltage levels are larger or smaller than the lower threshold voltage,
- detector means adapted to receive and process the first comparator signal and the second comparator signal and to generate a detector output signal having a first logic level when the incoming signal level is larger than the upper threshold voltage or smaller than the lower predetermined threshold voltage and having second logic level when the input signal level is between the upper and the lower threshold voltages,
- a controller adapted to receive a recovered clock signal from a CDR circuit to determine data bit periods of the incoming digital data bit stream, and adapted to, within each data bit period, detect the presence or absence of the first logic level in the detector output signal, and adapted to control the state of a LOS defect signal indicating absence or presence of the digital data bit stream based on detected first logic levels and predetermined criteria.
A method of determining a Loss of Signal (LOS) of an incoming electrical signal of a digital data bit stream, the method comprising the steps of:
- recovering a clock signal or a data bit signal of the digital data bit stream encoded or embedded in the digital data bit stream,
- comparing a voltage level of the incoming electrical signal to an upper threshold voltage,
- providing a first comparator signal indicating whether the voltage level is larger or smaller than the upper threshold voltage,
- comparing the input voltage level of the incoming electrical signal to a second threshold voltage,
- providing a second comparator signal indicating whether the voltage level is larger or smaller than the lower threshold voltage, processing the first comparator signal and the second comparator signal to generate an detector output signal having a first logic level when the input signal level is larger than the upper threshold voltage or smaller than the lower threshold voltage, and to generate a second logic level when the input signal level is between upper and the lower threshold voltages,
- determining data bit periods of the incoming digital data signal by a controller receiving the recovered clock signal or data bit signal,
- detecting, within each data bit period, the presence or absence of the first logic level in the detector output signal, and
- controlling a state of a LOS defect signal indicating absence or presence of the digital data stream based on detected first logic levels and predetermined criteria.
5 more elements
An intergrated circuit for receiving a signal of a digital data bit stream and determining a Loss of Signal (LOS) detection, comprising:
- a threshold circuit for determining whether or not the received signal is between upper and lower voltage thresholds;
- and
- a controller for outputting a LOS defect signal based on the determinations made by the detection circuit during a consecutive number of bit periods of a clock signal recovered from said received signal,
- wherein the threshold circuit generates an output having a first logic level when the received signal is not between the predetermined upper and lower threshold voltages and having a second logic level when the received signal is in between the predetermined upper and lower threshold voltages,
- wherein the controller comprised at least one Set-Reset Latch (SR-Latch) having a Set input terminal adapted to receive the detector output signal and having a Reset terminal adapted to receive an SR clock signal operating synchronous with respect to the recovered clock signal to reset the at least one SR-Latch at the beginning of each new data bit period, thereby adapting the at least one SR-Latch to detect the presence of the first logic level in the detector output signal in each bit period of the incoming digital data bit stream.
2 more elements
An integrated circuit for receiving a signal of a digital data bit stream and determining a Loss of Signal (LOS) detection, comprising:
- a threshold circuit for determining whether or not the received signal is between upper and lower voltage thresholds;
- and
- a controller for outputting a LOS defect signal based on the determinations made by the detection circuit during a consecutive number of bit periods of a clock signal recovered from said received signal,
- wherein the threshold circuit generates an output having a first logic level when the received signal is not between the predetermined upper and lower threshold voltages and having a second logic level when the received signal is in between the predetermined upper and lower threshold voltages,
- wherein the controller is adapted to count data bit periods in consecutive blocks of N data bits, N being an integer, and to determine for substantially each of the blocks of N bits, a valid bit count equaling the number of data bit periods wherein the presence of the first logic level has been detected, and further adapted to control the state of the LOS defect signal according to predetermined criteria of the controller and the valid count.
2 more elements
An integrated circuit for receiving a signal of a digital data bit stream and detecting Loss of Signal (LOS) events, comprising:
- a threshold circuit for generating an output signal having a low and high logic level, respectively, which indicates whether or not the received signal is between predetermined upper and lower voltage thresholds;
- at least one Set-Reset Latch (SR-Latch) for detecting the presence of a high logic level in the detector output signal in each bit period of a clock signal recovered from the received signal, wherein
- an LOS event is detected based on whether or not the SR-Latch detects a high logic level in one or more bit periods of the recovered clock signal.
An article of manufacture, comprising:
- a machine accessible medium comprising content that when accessed by a machine causes the machine to:
- recover a clock signal or a data bit signal of the digital data bit stream encoded or embedded in the digital data bit stream,
- compare a voltage level of the incoming electrical signal to an upper threshold voltage,
- provide a first comparator signal indicating whether the voltage level is larger or smaller than the upper threshold voltage,
- compare the input voltage level of the incoming electrical signal to the second threshold voltage,
- provide a second comparator signal indicating whether the voltage level is larger or smaller than the lower threshold voltage,
- process the first comparator signal and the second comparator signal to generate an detector output signal having a first logic level when the input signal level is larger than the upper threshold voltage or smaller than the lower threshold voltage, and to generate a second logic level when the input signal level is between upper and the lower threshold voltages,
- determine data bit periods of the incoming digital data signal by a controller receiving the recovered clock signal or data bit signal,
- detect, within each data bit period, the presence or absence of the first logic level in the detector output signal, and
- control a state of a LOS defect signal indicating absence or presence of the digital data stream based on detected first logic levels and predetermined criteria.
7 more elements
Dependencies are inferred from the claim text.