Calibration technique for memory devices
AssigneeMicron Technology, Inc.
InventorsBrian Johnson, Brent Keeth
Life of this patent
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Abstract
Disclosed is an improved start-up/reset calibration apparatus and method for use in a memory device One of a plurality of data paths is bit wise calibrated relative to a clock signal and thereafter others of the plurality of data paths are bit wise aligned to a previously calibrated data path to produce serial and parallel bit alignment on all data paths.
Claims104
A method of calibrating data paths of a memory device, said method comprising:
- calibrating a first data path of said memory device to align data present on said first data path relative to a clock signal for clocking in data on said first data path;
- and
- calibrating a second data path of said memory device to align data present on said second data path relative to said clock signal using calibrated data from said first data path.
A method of calibrating a plurality of data paths of a memory device comprising:
- calibrating a first data path of said memory device to align the timing of data present on said first data path relative to a clock signal for clocking in data on said first data path;
- and
- calibrating remaining data paths of said memory device to align data present on each of said remaining data paths with calibrated data on said first data path to achieve serial and parallel alignment of data on said first and remaining data paths.
A digital circuit for calibrating incoming data paths of a memory circuit, comprising:
- an incoming clock signal path on which a clock signal is transmitted;
- a first data path;
- a second data path;
- a control logic circuit connected to align data present on said first data path relative to said clock signal, said control logic circuit further aligning data present on said second data path relative to said clock signal by aligning data present on said second data path with aligned data on said first data path.
A semiconductor memory circuit, comprising:
- a memory module;
- a memory controller connected to said memory module;
- and
- a calibration circuit for calibrating data incoming to said memory module, said calibration circuit comprising:
- an incoming clock signal path on which a clock signal is transmitted;
- a first data path;
- a second data path;
- a control logic circuit connected to align data present on said first data path relative to said clock signal, said control logic circuit further aligning data present on said second data path relative to said clock signal by aligning data present on said second data path with aligned data on said first data path.
A processor-based system, comprising:
- a processor;
- an integrated memory circuit connected to said processor, said integrated memory circuit including a calibration circuit comprising:
- an incoming clock signal path on which a clock signal is transmitted;
- a first data path;
- a second data path;
- a control logic circuit connected to align data present on said first data path relative to said clock signal, said control logic circuit further aligning data present on said second data path relative to said clock signal by aligning data present on said second data path with aligned data on said first data path.
An embedded-memory processor-based system, comprising:
- a processor;
- a memory circuit formed on a same integrated circuit as said processor, said memory circuit including a calibration circuit comprising:
- an incoming clock signal path on which a clock signal is transmitted;
- a first data path;
- a second data path;
- a control logic circuit connected to align data present on said first data path relative to said clock signal, said control logic circuit further aligning data present on said second data path relative to said clock signal by aligning data present on said second data path with aligned data on said first data path.
Dependencies are inferred from the claim text.