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US 6,434,064 B1Granted
Semiconductor memory device having redundancy circuit for saving faulty memory cells
AssigneeKabushiki Kaisha Toshiba
InventorTakeshi Nagai
Life of this patent
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Abstract
In a semiconductor memory device comprising a redundancy circuit for saving a faulty memory cell, there are provided a plurality of fuse sets to which a flexible mapping redundancy technique is applied. For at least one of these plurality of fuse sets, there is used a row/column common saving fuse set configured so as to make it available for use in one of row saving and column saving. Even in the case where a number of row faults occur with a memory chip or in the case where a number of column faults occur, the setting of row saving or column saving of a row/column common saving fuse set is adjusted accordingly, whereby saving efficiency is improved, and high saving efficiency in a small area can be achieved.
Claims23
A semiconductor memory device comprising:
- a memory cell array comprising a plurality of memory cells arranged in a plurality of rows and in a plurality of columns, said memory cell array being divided into a plurality of sub-cell arrays;
- a row redundancy element and a column redundancy element disposed in correspondence to each of said sub-cell arrays;
- a normal row decoder for selecting a row of said memory cell array according to an input address;
- a normal column decoder for selecting a column of said memory cell array according to an input address;
- a plurality of information storing circuits each storing an address of a faulty memory cell contained in each memory cell array and storing mapping information indicating a correspondence between said each storing circuit and said row redundancy element or a correspondence between said each storing circuit and said column redundancy element, said information storing circuits being adopted to output a row saving control signal for replacing said faulty memory cell with said row redundancy element or a column saving control signal for replacing said faulty memory cell with said column redundancy element based on said mapping information and a match result in said case where said address of said faulty memory cell coincides with an input address;
- a control circuit for deactivating said normal row decoder according to said row saving control signal supplied from said information storing circuit;
- a spare row decoder activated according to said row saving control signal supplied from said information storing circuit, said spare row decoder selecting said row redundancy element;
- a control circuit for deactivating said normal column decoder according to said column saving control signal supplied from said information storing circuit;
- and
- a spare column decoder activated according to said column saving control signal supplied from said information storing circuit, said spare column decoder selecting said column redundancy element,
- wherein at least one of said plurality of information storing circuits is a row/column common information storing circuit that contains a first nonvolatile storage element capable of programming information on whether row saving or column saving is carried out by using said information storing circuit, and that is selectable for use in either one of said row saving and column saving.
8 more elements
A semiconductor memory device comprising:
- a memory cell array comprising a plurality of memory cells arranged in a plurality of rows and in a plurality of columns, said memory cell array being divided into a plurality of sub-cell arrays;
- a row redundancy element and a column redundancy element disposed in correspondence to each of said sub-cell array, and
- a plurality of information storing circuits each storing an address of a faulty memory cell contained in each memory cell array and storing mapping information indicating a correspondence between said each storing circuit and said row redundancy element or a correspondence between said each storing circuit and said column redundancy element, said information storing circuits being adopted to output a row saving control signal for replacing said faulty memory cell with said row redundancy element or a column saving control signal for replacing said faulty memory cell with said column redundancy element based on said match result and said mapping information in the case where said address of said faulty memory cell coincides with an input address;
- wherein at least one of said plurality of information storing circuits is a row/column common information storing circuit that contains a first nonvolatile storage element capable of programming information on whether row saving or column saving is carried out by using said information storing circuit, and that is selectable for use in either one of said row saving and column saving.
1 more element
Dependencies are inferred from the claim text.