Combined parallel adaptive equalizer/echo canceller

A method of providing parallel adaptive equalization and echo cancellation, comprising the steps of:

• receiving input signals at a plurality of transverse finite impulse filters;
• splitting the input signals at each transverse finite impulse filter into a plurality of tap signals;
• multiplying each of the tap signals for each transverse finite impulse filter by a tap coefficient to produce a tap output signal;
• receiving the tap output signals from each of the plurality of transverse finite impulse filters at an iterative pipeline;
• summing the received tap output signals from the plurality of transverse finite impulse filters and an output from one of a plurality of registers having an input and an output, the input of each register being coupled to an output of an adder and the output of each register being passed to an input of a next one of the adders in a pipeline manner according to a next cycle;
• and
• calculating updated tap coefficients using a coefficient processor, the updated tap coefficients calculated using an error signal and delayed versions of the input signal, wherein wherein an error register chain is provided to output the error signal.

A combined, parallel adaptive equalizer/echo canceller, comprising:

• a plurality of transverse finite impulse response filters, each filter receiving an input signal and providing a plurality of tap signals to a corresponding plurality of multipliers, wherein each multiplier provides a tap output signal resulting from the product of the tap signals and a tap coefficient;
• an iterative pipeline, coupled to the plurality of filters, the iterative pipeline comprising a plurality of registers and a plurality of adders, wherein the registers and the adders are coupled alternate to each other with an output of the registers being passed to an input of a next one of the adders in the iterative pipeline, and an output of the adders being passed to an input of a next one of the registers, each of the adders having a first set of inputs for receiving tap output signals from each of the plurality of transverse finite impulse response filters and a second input for receiving the output of one of the registers, the adders providing a sum signal representing a sum of the received tap output signals from each of the plurality of transverse finite impulse response filters and the output of one of the registers;
• and
• a coefficient processor, coupled to the filters, for calculating updated tap coefficients, the updated tap coefficients calculated using an error signal and delayed versions of the input signal, wherein wherein an error register chain is provided to output the error signal.