Method for bias rail buffering
AssigneeTexas Instruments Incorporated
InventorsKenneth W. Murray, Joel M. Halbert
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AssigneeTexas Instruments Incorporated
InventorsKenneth W. Murray, Joel M. Halbert
Estimating the term…
A bias rail buffer circuit and method in accordance with the present invention overcomes many shortcomings of the prior art. A bias rail buffer circuit for providing a reference signal is suitably configured to absorb external disturbances appearing on an output reference signal. A method for absorbing the external disturbances appearing at the output reference signal suitably includes the use of complementary transistors to source current and sink current to said output reference signal, depending on whether the external disturbances are providing a decrease or an increase to the output reference signal. The bias rail buffer circuit suitably includes an input transistor, a first pair of complementary transistors and a second pair of complementary transistors, such that the second pair of complementary transistors operate to source current and sink current to absorb external disturbances imparted on said output reference signal.
A method for providing a stable reference signal from a bias rail supply, said method comprising the steps of:
A method for providing a stable reference signal from a bias rail supply, said method comprising the steps of.
A method for providing a stable reference signal from a bias rail supply, said method comprising the steps of:
A method for providing a stable reference signal from a bias rail supply, said method comprising the steps of:
Dependencies are inferred from the claim text.