Digital fractional phase detector

A digital fractional phase detector comprising:

• a first input configured to receive a first clock signal;
• a plurality of delay elements in communication with the first input;
• a second input configured to receive a second clock signal;
• a plural of latch/registers in communication with the plurality of delay elements and the second input such that the plurality of latch/registers store a delayed replica of fist clock signal data in response to significant edge transitions associated with the second clock signal;
• a digital edge detector in communication with the plurality of latch/registers and configured to generate a time-to-digital rise-time signal associated with a timing of a positive transition of the first clock signal and further configured to generate a time-to digital fall-time signal associated with a timing of a negative transition of the first clock;
• a normalizer element responsive to the rise-time signal and the fall-time signal to generate a period-normalized fractional phase signal that is normalized to a clock period associated with the first clock signal;
• and
• an output, wherein the digital factional phase detector is responsive to the first and second clock signals such that it generates a fractional phase compensated signal therefrom at the output, wherein the fractional phase compensated signal affects a zero averaged phase difference between the first clock signal and the second clock signal.

A digital factional phase detector comprising:

• means for receiving a digitally-controlled voltage controlled oscillator (dVCO) clock signal;
• means for receiving a frequency reference clock signal and storing a snapshot of a delayed replica of said dVCO clock signal data in response to significant edge transitions associated with the frequency reference clock signal;
• means for retrieving the delayed replica of said dVCO clock signal data in response to the frequency reference clock signal and generating a rise-time sign and a fall-time signal therefrom;
• and
• means for receiving the rise-time signal and the fall-time signal and generating a period-normalized fractional phase signal therefrom.

A digital fractional phase detector comprising:

• first means for receiving a first clock signal, wherein the first receiving means comprises a plurality of delay elements selected from the group consisting of inverters, a tapped delay line, and buffers;
• second means for receiving a second clock signal, wherein the second receiving means comprises a plurality of latch/registers and coupled to said first means for storing a delayed replica of said first clock signal;
• a digital edge detecting means responsive to said first and second means for generating a rise-time signal associated with a positive transition of the first clock and further for generating a fall-time signal associated with a negative transition of the first clock;
• and
• means for receiving an accumulated frequency control word fractional phase signal and said rise-time and fall-time signals to generate a fractional phase compensated signal therefrom.

A digital fractional phase detector comprising:

• a plurality of delay elements connected in tandem, wherein each delay element has an input and an output, and further wherein the first delay element input is a VCO clock input;
• a plurality of latch/registers, wherein each latch/register has a first input connected to an output of a different delay element, and further wherein each latch/register has a second input configured to receive a common frequency reference clock signal, and further wherein each latch/register has an output;
• a digital edge detector having a plurality of inputs, wherein each edge detector input is connected to a different latch/register output, and further having a pair of outputs;
• a normalizer element having a pair of inputs connected to the pair of edge detector outputs, and further having an output;
• and
• a combinatorial element having an input connected to the output of the normalizer element and further having an output.

A digital factional phase detector comprising:

• means for receiving a digitally-controlled voltage controlled oscillator (dVCO) clock signal;
• means for receiving a frequency reference clock signal and storing a snapshot of a delayed replica of said dVCO clock signal data in response to significant edge transitions associated with the frequency reference clock signal;
• means for retrieving the delayed replica of said dVCO clock signal data in response to the frequency reference clock signal and generating a fit time-to-digital signal and a second time-to-digital signal therefrom;
• and
• means for receiving the first time-to-digital signal and the second time-to-digital signal and generating period-normalized factional phase signal therefrom.