Fir filter structure with time- varying coefficients and filtering method for digital data scaling

A method of transmitting first and second time discrete signals between source and sink systems wherein in first signal x(k) is generated by said source system at a first sampling rate fx and a second time discrete signal y(m) is generated by said sink system at a second sampling rate fy different from said first sampling rate fx, where fy=U/Dfx [k is an integer 0, 1, . . . k and m=┌kU/D┐+n], comprising the steps of:

• A. multiplying said first time discrete signal x(k) by each of the gi⊕D(n)coefficients, n=0, 1, . . . , (Q−1), each of said D sets of coefficients having q elements with the jth element, j=0, 1, . . . , (Q−1), equal to gi⊕D(j)=h(jD+(−iU) modulo D), where the function h denotes the coefficients of a FIR filter having coefficients with unit sample response length N and input index i=−∞ . . . 0, 1, . . . ∞, where Q=┌N/D┐ and N=length of filter h();
• B. accumulating said multiplied signals in each of a Q plurality of matrix delay elements having time delay of D/(Ufx);
• C. shifting said Q plurality of delayed signals to generate said second time discrete signal y(m) having a sampling rate fy=U/Dfx;
• and
• D. holding said summed signal y(m) in an output buffer.

Apparatus for converting the sampling rate of a digital input signal from fx, to ((U/D))fx, where U and D are integers, comprising

• A. an input lead, the digital input signal coupled to said input lead;
• B. a multiplier having an output and a first and second input terminals for supplying an output signal that is the product of the signals applied to said first and second input terminal, said input lead coupled to said second input terminal of said multiplier;
• C. a memory unit coupled to said first input of said multiplier for storing D sets of coefficients, gi⊕D(n), n=0, 1, . . . , (Q−1), each of said D sets of coefficients having q elements with the jth element, j=0, 1, . . . , (Q−1), equal to gi⊕D(j)=h(jD+(−iU) modulo D), where the function h denotes the coefficients of a FIR filter having coefficients with unit sample response length N and input index i=−∞ . . . 0, 1, . . . ∞;
• D. a sequencer coupled to said memory unit for sequentially transferring and selecting each coefficient set gi⊕D(n) coupled to said first input terminal of said multiplier;
• E. an adder coupled to the output of said multiplier for determining the output partial sums by summing the products supplied by said multiplier;
• and
• F. output buffer coupled to said adder for storing the accumulated output sample y(n).

A multistage apparatus having at least two stages for converting the sampling rate of a digital input signal from fx, to ((UaUb/DaDb))fx, where Ua, Ub, Da and Db are integers, comprising

• a first stage;
• and
• a second stage coupled to said first stage,
• wherein the first stage comprises
• an input lead, the digital input signal coupled to said input lead;
• a multiplier having an output and a first and second input terminals for supplying an output signal that is the product of the signals applied to said first and second input terminal, said input lead coupled to said second input terminal of said multiplier;
• a memory unit coupled to said first input of said multiplier for storing Da sets of coefficients, gai⊕D(n), n=0, 1 . . . , (Qa−1 ), each of said Da sets of coefficients having Qa elements with the jth element, j=0, 1, . . . , (Qa−1) , equal to gai⊕D(j)=ha(jDa+(−iUa) modulo Da) where the function ha denotes the coefficients of a FIR filter having coefficients with unit sample response length Na and input index i=−∞ . . . 0, 1, . . . ∞;
• a sequencer coupled to said memory unit for sequentially transferring and selecting each coefficient set gai⊕D(n) coupled to said first input terminal of said multiplier;
• an adder coupled to the output of said multiplier for determining the output partial sums by summing the products supplied by said multiplier;
• and
• output buffer coupled to said adder for
• storing the accumulated output sample y(n);
• and wherein the second stage comprises
• a delay coupled to said first stage for supplying a delay to the accumulated output sample y(n);
• a switch coupled to said delay;
• a multiplier having an output and a first and second input terminals for supplying an output signal that is the product of the signals applied to said first and second input terminal, said first input terminal coupled to said switch;
• a memory unit coupled to said second input of said multiplier for storing Db sets of coefficients, gbi⊕U(n) , n=0, 1, . . . , (Qb−1), each of said Db sets of coefficients having Qb elements with the jth element, j=0, 1, . . . , (Qb−1), equal to gbi⊕U(j)=hb(jUb+(iDb) modulo Ub), where the function hb denotes the coefficients of a FIR filter having coefficients with unit sample response length Nb and input index i=−∞ . . . 0, 1, . . .∞;
• and
• an adder coupled to the output of said multiplier for determining the output partial sums by summing the products supplied by said multiplier.

A multistage apparatus having at least two stages for converting the sampling rate of a digital input signal from fx, to ((UaUb/DaDb) ) fx, where Ua, Ub, Da and Db are integers, comprising

• a first stage;
• and
• a second stage coupled to said first stage,
• wherein the first stage comprises
• a delay for supplying a delay to the output signal;
• a switch coupled to said delay;
• a multiplier having an output and a first and second input terminals for supplying an output signal that is the product of the signals applied to said first and second input terminal, said first input terminal coupled to said switch;
• a memory unit coupled to said second input of said multiplier for storing Db sets of coefficients, gbi⊕U(n), n=0, 1, . . . , (Qb−1), each of said Db sets of coefficients having Qb elements with the jth element, j=0, 1, . . . , (Qb−1), equal to gbi⊕U(j)=hb (jUb+(iDb) modulo Ub), where the function hb denotes the coefficients of a FIR filter having coefficients with unit sample response length Nb and input index i=−∞ . . . 0, 1, . . . ∞;
• and
• an adder coupled to the output of said multiplier for determining the output partial sums by summing the products supplied by said multiplier;
• and
• wherein the second stage comprises
• an input lead, the digital input signal coupled to said first stage;
• a multiplier having an output and a first and second input terminals for supplying an output signal that is the product of the signals applied to said first and second input terminal, said input lead coupled to said second input terminal of said multiplier;
• a memory unit coupled to said first input of said multiplier for storing Da sets of coefficients, gai⊕D(n), n=0, 1, . . . , (Qa−1) , each of said Da sets of coefficients having Qa elements with the jth element, j=0, 1, . . . , (Qa−1), equal to gai⊕D(j)=ha(jDa+(−iUa) modulo Da) where the function ha denotes the coefficients of a FIR filter having coefficients with unit sample response length Na and input index i=−∞ . . . 0, 1, . . . ∞;
• a sequencer coupled to said memory unit for sequentially transferring and selecting each coefficient set gai⊕D(n) coupled to said first input terminal of said multiplier;
• an adder coupled to the output of said multiplier for determining the output partial sums by summing the products supplied by said multiplier;
• and
• output buffer coupled to said adder for storing the accumulated output sample y(n).