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US 6,426,908 B1Granted
Semiconductor memory device with reduced current consumption in data hold mode
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorHideto Hidaka
Life of this patent
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Abstract
A power supply circuit generating a power supply voltage for refresh-related circuitry and a power supply circuit for column-related/peripheral control circuitry are controlled by a power supply control circuit to be put in different power supply voltage supplying states in a self refresh mode. In the self refresh mode, only self refresh-related circuitry receives a power supply voltage to perform refresh operation. A reduced current consumption can be achieved in the self refresh mode while fast access operation is not deteriorated.
Claims17
A semiconductor device comprising:
- a plurality of memory cells having data stored therein and refreshed within a predetermined period of time;
- refresh-related circuitry for refreshing the data stored in said plurality of memory cells in a refresh mode;
- peripheral circuitry different from said refresh-related circuitry, for performing at least an operation related to accessing to said plurality of memory cells;
- a first power source circuit for supplying an operating power source voltage to said refresh-related circuitry;
- a second power source circuit provided separately from said first power source circuit, for supplying an operating power source voltage to said peripheral circuitry;
- and
- power supply control circuitry responsive to an operation mode designation signal for adjusting a voltage supply of at least said second power source circuit, said power supply control circuitry setting the first and second power source circuits in different voltage supplying states from each other when said operation mode designation signal designates said refresh mode and setting the first and second power source circuits in an identical voltage supplying state when said operation mode designation signal designates a normal mode different from said refresh mode.
4 more elements
A semiconductor device comprising:
- a memory cell array including a plurality of memory cells and having a predetermined storage capacity, said plurality of memory cells each having data stored therein and refreshed within a predetermined period;
- means for storing a refresh region designation address designating a region to be refreshed of said memory array when an operation mode designation signal designates a refresh mode;
- a refresh address generation circuit for generating a refresh address addressing a memory cell to be refreshed in the region designated by said refresh region designation address when said operation mode designation signal designates said refresh mode;
- a refresh timer outputting a refresh request requesting refreshing of data of said plurality of memory cells at a prescribed period in said refresh mode;
- and
- refresh-related circuitry responsive to said refresh request, for refreshing data of a memory cell selected from said plurality of memory cells according to the refresh address from said refresh address generation circuit.
3 more elements
Dependencies are inferred from the claim text.