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US 6,426,743 B1Granted
Shift register
AssigneeLG. Philips LCD Co., Ltd.
InventorsJu Cheon Yeo, Sang Young Yoon, Jin Sang Kim
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AssigneeLG. Philips LCD Co., Ltd.
InventorsJu Cheon Yeo, Sang Young Yoon, Jin Sang Kim
Estimating the term…
In a shift register for driving a pixel row in a liquid crystal display device a plurality of stages are connected: to a high level voltage source, a low level voltage source and a phase-delayed clock signal generator; to row lines; and in cascade, with respect to a scanning signal, for charging and discharging the row lines. Each stage of the shift register has a pull-up transistor, a pull-down transistor, and first to fourth transistors. The pull-up transistor has a control electrode and a conduction path connected between the first clock signal line and the output terminal. The pull-down transistor has a control electrode and a conduction path connected between the low level voltage line and the output terminal. The first and second transistors have conduction paths connected in series between the input terminal and the control electrode of the pull-up transistor, and each has a control electrode connected commonly to the second clock signal line. The first and second transistors allow a voltage to be charged on the control electrode of the pull-up transistor. The third and fourth transistors have conduction paths connected in series between the third clock signal line and the control electrode of the pull-down transistor, and each has a control electrode connected commonly to the third clock signal line. The third and fourth transistors allow a voltage to be charged on the control electrode of the pull-down transistor.
A shift register circuit comprising a plurality of cascaded stages connected to a start pulse input line and driving sequentially a plurality of row lines, each of the stages having an input terminal, an output terminal, a low level voltage line and being connected to first to third clock signal lines, the input terminal receiving an output signal of a previous stage, and the output terminal being connected to a row line, each one of the stages comprising:
A shift register including a plurality of cascaded stages connected to a start pulse input line and driving sequentially a plurality of row lines, each of the stages having an input terminal, an output terminal, a low level voltage line and being connected to first to third clock signal lines, the input terminal receiving an output signal of a previous stage, the output terminal being connected to a row line, each one of the stages comprising:
In a shift register stage having a low level voltage line, an input terminal, and an output terminal, and being connected to first to third clock signal lines, a pull-up transistor being disposed between the output terminal and the first clock signal line, and a pull-down transistor being disposed between the output terminal and the low level voltage line, a method of delaying a start pulse receiving at the input terminal by a clock period to produce an output pulse at the output terminal, said method comprising:
Dependencies are inferred from the claim text.