Duty-cycle correction circuit
AssigneeInternational Business Machines Corporation
InventorsShiu C. Ho, David W. Blum
Life of this patent
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Abstract
A duty-cycle correction circuit corrects a clock with arbitrary duty-cycle to a 50% duty-cycle clock, with its original frequency. The device acts to translate a non-50% duty-cycle clock to an accurate 50% duty-cycle clock by utilizing a divide-by-2 frequency divider and a multiply-by-2 clock doubler to achieve conversion. The duty-cycle correction circuit increases the translation back to its original frequency while using an analog negative feedback to maintain an accurate 50% duty cycle.
Claims6
A duty-cycle correction circuit providing an accurate 50% duty cycle clock signal from an input clock signal having a frequency fc and a non-50% duty cycle, said circuit comprising:
- a divide-by-two frequency divider receiving the input clock signal and outputting a signal having a frequency fc/2 with a 50% duty cycle;
- a current controlled delay block receiving the output signal from the divide-by-two frequency divider and outputting a signal having a frequency fc/2 with a 50% duty cycle delayed by a time proportional to a current control signal;
- an exclusive OR gate receiving the output signals of the divide-by-two frequency divider and the current controlled delay block and outputting a signal having a frequency fc and a 50% duty cycle;
- a first low pass filter receiving the output signal of the exclusive OR gate and producing a first d.c. voltage signal;
- a second low pass filter receiving the output signal from the divide-by-two frequency divider and outputting a second d.c. voltage signal;
- an operational amplifier receiving the first and second d.c. voltages and outputting a voltage signal proportional to a difference between the first and second d.c. voltages;
- and
- a voltage controlled current source responsive to the output voltage signal of the operational amplifier for generating the current control signal to the current controlled delay block.
A method of translating a non-50% duty cycle clock signal having a frequency fc to an accurate 50% duty cycle clock signal, said method comprising the steps of:
- dividing the input clock signal by two and outputting a signal having a frequency fc/2 with a 50% duty cycle;
- delaying the signal having a frequency fc/2 with a 50% duty cycle by a time proportional to a current control signal;
- performing an exclusive OR function on the signal having a frequency fc/2 with a 50% duty cycle the delayed signal having a frequency fc/2 with a 50% duty and outputting a signal having a frequency fc and a 50% duty cycle;
- low pass filtering an output signal of the exclusive OR function to produce a first d.c. voltage;
- low pass filtering the signal having a frequency fc/2 with a 50% duty cycle to produce a second d.c. voltage;
- comparing the first and second d.c. voltages to produce a voltage signal proportional to a difference between the first and second d.c. voltages;
- and
- generating the current control signal as a function of the voltage signal proportional to a difference between the first and second d.c. voltages, the current control signal controlling the delay of the signal having a frequency fc/2 with a 50% duty cycle.
Dependencies are inferred from the claim text.