Architecture for field programmable gate array

A logic cell for a programmable application specific integrated circuit, said logic cell comprising:

• a combinatorial logic circuit having a plurality of input leads and an output lead;
• a first sequential logic element having a data input lead, a clock input lead, and a data output lead, said data input lead of said first sequential logic element being selectively coupled to said output lead of said combinatorial logic circuit, said data output lead of said first sequential logic element extending from said logic module and into said programmable interconnect structure;
• and
• a second sequential logic element having a data input lead, a clock input lead, and a data output lead, said data input lead of said second sequential logic element being selectively coupled to said output lead of said combinatorial logic circuit, said data output lead of said second sequential logic element extending from said logic module and into said programmable interconnect structure.

A programmable device, comprising:

• a programmable interconnect structure;
• and
• a plurality of logic modules, each of said logic modules having at least one output lead and a driver coupled between at least one output lead and said programmable interconnect structure, said driver comprising:
• an inverter having an input lead and an output lead, said input lead of said inverter coupled to said output lead of said logic module,
• a protection transistor having a first terminal, a second terminal and a gate terminal, said first terminal coupled to said output lead of said inverter, said second terminal coupled to said programmable interconnect structure;
• a primary charge pump coupled to said gate;
• and
• a secondary charge pump coupled to said primary charge pump and to said gate terminal of said protection transistor.

A programmable device comprising:

• an array of logic cells;
• a programmable interconnect structure coupled to said logic cells;
• an I/O circuit comprising:
• an I/O pad;
• and
• an output register having an input terminal coupled to said programmable interconnect structure and an output terminal coupled to said I/O pad and said programmable interconnect structure,
• wherein said I/O circuit further comprises:
• a multiplexer having a first data terminal coupled to said output terminal of said output register and a second data terminal coupled directly to said input terminal of said output register, and an output terminal coupled to said I/O pad.

A programmable device comprising:

• an array of logic cells;
• a programmable interconnect structure coupled to said logic cells;
• an I/O circuit comprising:
• an I/O pad;
• and
• an output register having an input terminal coupled to said programmable interconnect structure and an output terminal coupled to said I/O pad and said programmable interconnect structure,
• wherein said I/O circuit further comprises:
• a buffer having an input terminal coupled to said output terminal of said output register and an output terminal coupled to said I/O pad, said buffer having an enable terminal;
• and
• an output enable register having an input terminal coupled directly to said programmable interconnect structure and an output terminal coupled to said enable terminal of said buffer.

A programmable device comprising:

• an array of logic cells;
• a programmable interconnect structure coupled to said logic cells;
• an I/O circuit comprising:
• an I/O pad;
• and
• an output register having an input terminal coupled to said programmable interconnect structure and an output terminal coupled to said I/O pad and said programmable interconnect structure,
• wherein said I/O circuit further comprises a buffer with an adjustable slew rate, said buffer comprising an input terminal coupled to said output terminal of said output register and an output terminal coupled to said I/O pad and a slew rate control terminal coupled to said programmable interconnect structure.

A programmable device comprising:

• an array of logic cells;
• a programmable interconnect structure coupled to said logic cells;
• an I/O circuit comprising:
• an I/O pad;
• an input register having an input terminal coupled to said I/O pad and an output terminal coupled to said programmable interconnect structure;
• an output register having an input terminal coupled to said programmable interconnect structure and an output terminal coupled to said I/O pad;
• and
• a buffer disposed between said output terminal of said output register and said I/O pad, said buffer having an input terminal coupled to said output terminal of said output register and an output terminal coupled to said I/O pad, said buffer having an enable terminal;
• and
• an output enable register having an input terminal coupled to said programmable interconnect structure and an output terminal coupled to said enable terminal of said buffer.

A programmable device comprising:

• an array of logic cells;
• a programmable interconnect structure coupled to said logic cells;
• an I/O circuit comprising:
• an I/O pad;
• an output register having an input terminal coupled to said programmable interconnect structure and an output terminal;
• and
• a buffer with an adjustable slew rate, said buffer comprising an input terminal coupled to said output terminal of said output register and an output terminal coupled to said I/O pad and a slew rate control terminal coupled to said programmable interconnect structure.

A programmable device comprising:

• an array of logic cells;
• a programmable interconnect structure coupled to said logic cells;
• an I/O circuit comprising:
• an I/O pad;
• an input register having an input terminal and an output terminal coupled to said programmable interconnect structure;
• a multiplexer having a first data terminal coupled to said I/O pad, a second data terminal, and an output terminal coupled to said input terminal of said input register;
• and
• a differential translator having a first input terminal coupled to said I/O pad, a second input terminal coupled to a voltage reference source, and an output terminal coupled to said second data terminal of said multiplexer.

A field programmable gate array, comprising:

• an array of logic cells divided into quadrants;
• a clock pad;
• and
• a clock network coupled to said clock pad, said clock network having clock buses extending into the approximate center of each quadrant and bisecting each quadrant of said array of logic cells.

A field programmable gate array, comprising:

• an array of logic cells;
• a clock network programmably coupled to said logic cells, said clock network providing a clock signal to selected logic cells;
• a phase locked loop circuit coupled to said clock network, said phase locked loop circuit comprising:
• a first programmable divide by n circuit receiving said clock signal having an input terminal coupled to said clock network, and having an output terminal;
• a phase detector having a first input terminal coupled to said output terminal of said first programmable divide by n circuit, and having a second input terminal and an output terminal;
• a low pass filter having an input terminal coupled to said output terminal of said phase detector and having an output terminal;
• a voltage controlled oscillator having an input terminal coupled to said output terminal of said low pass filter and having an output terminal;
• a second programmable divide by n circuit having an input terminal coupled to said output terminal of said voltage controlled oscillator, and having an output terminal coupled to said clock network;
• and
• a third programmable divide by n circuit having an feedback terminal coupled to said clock network and having an output terminal coupled to said second input terminal of said phase detector.

A field programmable gate array comprising:

• an array of logic cells;
• routing resources having antifuses programming coupling said logic cells, wherein said array of logic cells and routing resources are divided into at least a first subsection and a second subsection;
• a plurality of horizontal programming cells coupled to each subsection, wherein a first set of horizontal programming cells is coupled to said first subsection and a second set of horizontal programming cells is coupled to said second subsection;
• a plurality of vertical programming cells, wherein a first set of vertical programming cells is coupled to said first subsection and a second set of vertical programming cells is coupled to said second subsection;
• a plurality of power buses, a first set of power buses coupled to said first set of horizontal programming cells, a second set of power buses coupled to said second set of horizontal programming cells, a third set of power buses coupled to said first set of vertical programming cells, and a fourth set of power buses coupled to said second set of vertical programming cells.

A field programmable gate array comprising:

• an array of logic cells divided into quadrants;
• a set of horizontal programming cells coupled to and bisecting each quadrant;
• a set of vertical programming cells coupled to and bisecting each quadrant, such that a pair of horizontal programming cells and vertical programming cells subdivides each quadrant into subquadrants;
• and
• a plurality of power buses, wherein each set of horizontal programming cells and each set of vertical programming cells is coupled to a different set of power buses.

A programmable device comprising:

• at least one antifuse;
• a high voltage programming source switchably coupled to said antifuse;
• a low voltage programming source switchably coupled to said antifuse;
• a first NMOS transistor disposed between said high voltage programming source and said antifuse;
• a first PMOS transistor disposed between said high voltage programming source and said antifuse, said first PMOS transistor being in parallel with said first NMOS transistor;
• and
• a control circuit coupled to said first NMOS transistor and said first PMOS transistor, said control circuit switching said first NMOS transistor and said first PMOS transistor on and off substantially simultaneously.

A method of programming an antifuse in a programmable device, said method comprising:

• switchably coupling said antifuse to a high voltage programming source through a first N channel transistor;
• switchably coupling said antifuse to said high voltage programming source through a first P channel transistor in parallel with said first N channel transistor;
• switchably coupling said antifuse to a low voltage programming source through a second N channel transistor;
• and
• switchably coupling said antifuse to said low voltage programming source through a second P channel transistor in parallel with said first N channel transistor.

A programmable device comprising:

• an array of logic cells;
• a programmable interconnect structure coupled to said logic cells;
• an I/O circuit;
• at least one I/O control pad;
• and
• a multiplexer having a first data terminal coupled to said at least one I/O control pad, a second data terminal coupled to said programmable interconnect structure, and an output terminal coupled to said I/O circuit and said programmable interconnect structure.