Semiconductor device and memory module

A semiconductor storage device comprising:

• two memory chips sealed by a sealing member in a state where their back surfaces are placed one over the other,
• wherein each of said two memory chips are divided into a plurality of memory areas,
• wherein each memory chip is subjected to memory accesses to activate ones of said memory areas in 2-bit data units, thereby to subject said two memory chips to memory accesses in 4-bit data units, and
• wherein positions of activated memory areas are different on the surfaces of said two memory chips placed on each other.

A semiconductor storage device comprising:

• first and second memory chips;
• a sealing member which seals said first and second memory chips where back surfaces of said first and second memory chips are placed one over the other;
• first and second leads which extend from a first latus of said sealing member to the inside and outside of said sealing member;
• and
• third and fourth leads which extend from a second latus of said sealing member opposite to said first latus, to the inside and outside of said sealing member,
• wherein each of said first and second memory chips includes first, second, third and fourth terminals for outputting data, which terminals are arranged along a straight line which is parallel to longer latera of said each of said first and second memory chips and passes through the central parts of shorter latera thereof, on a circuit forming surface of said each of said first and second memory chips,
• wherein the second terminal is arranged at a position nearer to the first terminal between said first terminal and third terminal,
• wherein the third terminal is arranged at a position nearer to the fourth terminal between said second terminal and fourth terminal,
• wherein the first lead and the fourth lead are arranged at positions which oppose said straight line held therebetween,
• wherein the second lead and the third lead are arranged at positions which oppose said straight line held therebetween, and
• wherein each of said first and second memory chips outputs data in 2-bit data units by employing either of the first and second terminals, and either of the third and fourth terminals, thereby to output data from the first, second, third and fourth leads in 4-bit data units.

A semiconductor storage device comprising:

• first and second memory chips;
• a sealing member which seals said first and second memory chips in a state where their back surfaces are placed one over the other;
• a plurality of leads for addresses, which extend inside and outside said sealing member;
• and
• a plurality of leads for data, which extend inside and outside said sealing member,
• wherein each of said leads for addresses is bifurcated within said sealing member, bifurcated leads being respectively extending over front surfaces of said first and second memory chips,
• wherein each of said leads for data is extended over the front surface of at least one of said first and second memory chips,
• wherein each of said first and second memory chips includes a plurality of address terminals and a plurality of data terminals on its front surface,
• wherein corresponding address terminals of said first and second memory chips are connected in common with the bifurcated leads for addresses through pieces of wire, respectively,
• wherein said data terminals on the first memory chip and said data terminals on the second memory chip are isolated and connected to corresponding leads for data through pieces of wire and
• wherein data are outputted in 2-bit units from each of said first and second memory chips, thereby to output data from said leads for data in 4-bit units.