Unit for processing numeric and logic operations for use in central processing units (cpus), multiprocessor systems, data-flow processors (dsps), systolic processors and field programmable gate arrays (epgas)

A configurable data processor, comprising:

• a plurality of configurable units for processing numerical and logic operations, the plurality of configurable units arranged in a multi-dimensional pattern, each of the plurality of configurable units capable of operating as at least one of a data receiver and a data transmitter, each of the plurality of configurable units including
• a programmable arithmetic and logic unit for performing mathematical and logical functions, and
• a synchronization unit in communication with the programmable arithmetic and logic unit for synchronizing the configurable unit with at least another of the plurality of configurable units, the synchronization unit for receiving handshake signals from at least one of the plurality of other configurable units, at least one of the other configurable units being a non-next-neighbor of the configurable unit in the multidimensional pattern, and for transmitting handshake signals to at least one of the plurality of other configurable units, and
• a state unit in communication with the programmable arithmetic and logic unit, the state unit for providing state information to a program load unit, the program load unit controlling a reconfiguration of the configurable unit;
• wherein when one of the plurality of configurable units operates as the data receiver, it acknowledges data received by transmitting a data received signal to another one of the plurality of configurable units operating as the data transmitter.

A configurable unit for processing numerical and logic operations, the configurable unit being controlled by a program load unit, the configurable unit comprising:

• a programmable arithmetic and logic unit for performing a plurality of basic mathematical and logic functions;
• a first plurality of registers in communication with the programmable arithmetic and logic unit for storing data relating to a function of the configurable unit and data relating to an interconnection of units within the configurable unit;
• a first state machine for controlling the programmable arithmetic and logic unit;
• at least one register, in communication with at least the programmable arithmetic and logic unit, for storing at least one operand of the programmable arithmetic and logic unit, at least one of the at least one register including a shift register and at least one of the at least one register being a result register, the result register storing result data;
• a multiplexer having an input coupled at least to an output of the result register and an output coupled an input of the programmable arithmetic and logic unit, the multiplexer providing the result data to the input of the programmable arithmetic and logic unit;
• a bus unit, in communication with the result register, for providing a pick-up of data from a bus system and for providing the result data to the bus system, the bus unit being capable of sending data to a plurality of receiving units and automatically synchronizing the plurality of receiving units;
• a second state machine, in communication with at least the first state machine, for automatically controlling a sequence of bus transfers occurring over the bus system and including a plurality of handshake lines;
• and
• a state-back unit, in communication with the result register, for providing to the program load unit a processing status and a reconfigurability status of the configurable unit, wherein any one of a configuration and a reconfiguration of the configurable unit has no interfering effect on any other configurable unit that is in communication with the program load unit.

A method of synchronizing data flow in a data flow processor, the data flow processor including processing array elements arranged in a multi-dimensional pattern, comprising the steps of:

• transmitting a ready signal by a first element of the processing array elements;
• receiving the ready signal by a second element of the processing array elements,the second element of the processing array elements being a non-next-neighbor of the first element of the processing array elements;
• after receiving the ready signal, transmitting an acknowledgment signal from the second element to the first element only if the second element is in a first state, the first state being a state in which the second element is capable of accepting data;
• entering a wait state by the first element if the acknowledgment signal is not received within one clock cycle;
• and
• processing by the first element a next data after the first acknowledgment signal is received.

A configurable data processor, comprising:

• a plurality of configurable units arranged to process numerical and logic operations, each of the plurality of configurable units capable of operating as at least one of a data receiver and a data transmitter;
• a plurality of buses, each bus arranged to connect at least three of the plurality of configurable units;
• wherein each of the plurality of configurable units includes
• a programmable arithmetic and logic unit arranged to perform mathematical and logical functions, and
• a synchronization unit in communication with the programmable arithmetic and logic unit and arranged to synchronize the configurable unit with at least another of the plurality of configurable units, the synchronization unit arranged to receive handshake signals from at least one of the plurality of other configurable units via at least one of the plurality of buses, and arranged to transmit handshake signals to at least one of the plurality of other configurable units via the at least one of the plurality of buses, and
• a state unit in communication with the programmable arithmetic and logic unit, the state unit for providing state information to a program load unit, the program load unit controlling a reconfiguration of the configurable unit, and
• wherein when one of the plurality of configurable units operates as the data receiver, it acknowledges data received by transmitting a data received signal via one of the plurality of buses to another one of the plurality of configurable units operating as the data transmitter.

A method of synchronizing data flow in a data flow processor, the data flow processor including processing array elements arranged in a multi-dimensional pattern and a plurality of external buses, each bus arranged to link at least three of the processing array elements, comprising the steps of:

• transmitting a ready signal by a first element of the processing array elements via one of the plurality of external buses;
• receiving the ready signal by a second element of the processing array elements;
• after receiving the ready signal, transmitting an acknowledgment signal from the second element to the first element via the external bus only if the second element is in a first state, the first state being a state in which the second element is capable of accepting data;
• entering a wait state by the first element if the acknowledgment signal is not received within one clock cycle;
• and
• processing by the first element a next data after the first acknowledgment signal is received.