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US 6,424,582 B1Granted
Semiconductor memory device having redundancy
AssigneeMitsubishi Denki Kasbushiki Kaisha
InventorsTsukasa Ooishi, Hideto Hidaka
Life of this patent
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Abstract
A redundancy determination circuit receiving an address signal from an address bus outputs a replacement signal when a set address matches the received address. A multiplexer activates any spare activation signal line that activates respective redundant memory arrays provided in the row direction and column direction in a memory bank at a predetermined timing. The redundancy determination circuit can set the address to use a redundant memory array in either the row direction or the column direction. Therefore, the number of redundancy determination circuits can be reduced.
Claims18
A semiconductor memory device comprising:
- a plurality of memory cell blocks each including a plurality of regular memory cells;
- a redundant memory cell;
- and
- a redundancy determination circuit provided in common to at least two of said plurality of memory cell blocks and controlled by a block signal for discriminating from said at least two of said plurality of memory cell blocks, to activate a select operation of the redundant memory cell when an address signal matches a preset defective address in said plurality of regular memory cells.
1 more element
A semiconductor memory device comprising:
- a plurality of memory cell blocks each including regular memory cells and redundant memory cells;
- a plurality of program circuits each for programming a defective address in the regular memory cells and comparing an address signal with the defective address;
- an encoder for changing an accessed block in response to the comparison results of said plurality of program circuits;
- and
- a plurality of decoders provided corresponding to said plurality of memory cell blocks, each for decoding an output from said encoder and selecting the redundant memory cell in a corresponding memory cell block according to the decoding result.
2 more elements
A semiconductor memory device comprising:
- a plurality of memory cell blocks each including a plurality of regular memory cells arranged in rows and columns and a redundant row of redundant memory cells;
- and
- a redundancy determination circuit provided in common to at least two of said plurality of memory cell blocks and controlled by a block signal for discriminating from said at least two of said plurality of memory cell blocks, to activate a select operation of the redundant row when an address signal matches a preset defective address in said plurality of regular memory cells.
A semiconductor memory device comprising:
- a plurality of memory cell blocks each including regular memory cells and redundant memory cells;
- a plurality of program circuits each for programming a defective address in the regular memory cells and comparing an address signal with the defective address;
- a logic circuit for changing an accessed block in response to the comparison results of said plurality of program circuits;
- and
- a plurality of decoders provided corresponding to said plurality of memory cell blocks, each for decoding an output from said logic circuit and selecting the redundant memory cell in a corresponding memory cell block according to the decoding result.
2 more elements
A semiconductor memory device comprising:
- a plurality of memory cell blocks each including regular memory cells and redundant memory cells;
- a redundancy determination unit including a redundancy program circuit for programming a defective address in the regular memory cells and comparing an address signal with the defective address;
- an encoder for changing an accessed block in response to the comparison results of said redundancy determination unit;
- and
- a plurality of decoders provided corresponding to said plurality of memory cell blocks, each for decoding an output from said encoder and selecting the redundant memory cell in a corresponding memory cell block according to the decoding result.
2 more elements
A semiconductor memory device comprising:
- a plurality of memory blocks of which stored data is accessible according to an external signal transmitting information including first and second extraction codes;
- a plurality of redundancy units for operating in place of a defective portion present in said plurality of memory blocks;
- and
- a redundancy determination unit determining usage of said plurality of redundancy units, including a plurality of first program units and a plurality of second program units,
- said redundancy determination unit extracting a first portion from said plurality of first program units according to said first extraction code and extracting a second portion from said plurality of second program units according to said second extraction code, and determining one of said plurality of redundancy units corresponding to said external signal according to said extracted first and second portions.
2 more elements
Dependencies are inferred from the claim text.