Successive approximation algorithm-based architectures and systems

A method for calibrating a digital memory with capacitor weights to be used in subsequent approximation of unknown voltages, comprising:

• generating a first bit sequence (FBS) representing the switched on states of each of a plurality of capacitors (PCS) in a predetermined capacitor array (CA) of a charge redistribution digital-to-analog converter (CRDAC);
• increasing the numerical value (NV) of said FBS;
• sampling a voltage to said CA by applying a reference voltage to those of said PCSs which are switched on consistently with said FBS;
• successively generating the result bits of a second bit sequence (SBS) during successive approximation, by identifying the switched-on states of particular capacitors in said CRDAC which are able substantially to nullify the charge on the CRDAC including the increased charge due to the increase made in the NV of said FBS;
• determining the digital weights corresponding to said identified capacitors able to cancel the applied charge;
• and
• storing said determined digital weights in a digital memory for subsequent retrieval to effect successive approximation operation to determine the value of an input unknown voltage level.

A method for calibrating a digital memory having capacitor weights to be used in approximating an unknown voltage signal, the method comprising:

• generating a first bit sequence, having a first numerical value and representing switched-on capacitor states for a selected first sub-array of capacitors, drawn from an array of capacitors that are part of a charge redistribution digital-to-analog converter (CRDAC), where the CRDAC has an accumulated charge corresponding to the first numerical value;
• increasing the numerical value of the first bit sequence by a selected increment to obtain a second numerical value;
• sampling a voltage signal provided for the capacitors in the first sub-array by applying a reference voltage to each switched-on capacitor in the first sub-array;
• successively generating digital bits of a second bit sequence by identifying a second sub-array of capacitors, drawn from the array of capacitors, that substantially nullify an accumulated charge on the CRDAC corresponding to the second numerical value, when each capacitor in the second sub-array is switched on;
• and
• determining and storing a digital weight associated with each capacitor in the second sub-array.