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US 6,423,615 B1Granted
Silicon wafers for CMOS and other integrated circuits
AssigneeIntel Corporation
InventorsKramadhati V. Ravi, Li Ling, Sing-Chung S. Hu
Life of this patent
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Abstract
Techniques include heating a substantially uniformly boron-doped wafer to achieve a significantly increased resistivity in a near-surface region of the water and forming at least one electrical circuit element in the near-surface region.
Claims27
A method of manufacturing a semiconductor wafer, the method comprising:
- growing a silicon ingot substantially uniformly doped with boron, wherein the ingot has a resistivity in a range of about 10 to 1,000 milli-ohm-centimeter;
- slicing the ingot into individual wafers;
- heating at least one of the wafers in an atmosphere containing hydrogen at a temperature of at least about 1,000° C. to achieve a significantly increased resistivity in a near-surface region of the at least one of the wafers;
- and
- fabricating one or more electrical circuit elements in the near-surface region after the heating.
2 more elements
A method of manufacturing a semiconductor integrated circuit, the method comprising:
- heating a substantially uniformly boron-doped wafer in an atmosphere containing hydrogen at a temperature of at least about 1,000° C. to achieve a significantly increased resistivity in a near-surface region of the at least one wafer, wherein prior to the heating, the wafer has a resistivity in a range of about 10 to 1,000 milli-ohm-centimeter;
- and
- fabricating at least one electrical circuit element in the near-surface region.
A method comprising:
- heating a substantially uniformly boron-doped wafer to achieve a significantly increased resistivity in a near-surface region of the wafer;
- and
- subsequently forming at least one electrical circuit element in the near-surface region.
Dependencies are inferred from the claim text.