Use of DARC and BARC in flash memory processing
AssigneeMicron Technology, Inc.
InventorRichard D. Holscher
Life of this patent
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Abstract
A method of using dielectric anti-reflective coating (DARC) in conjunction with bottom anti-reflective coating (BARC) to form an anti-reflective barrier layer is provided. The anti-reflective layer conforms to the topography of the substrate surface and is adapted to function effectively in both annealed and unannealed states. The method of using DARC in combination with BARC also inhibits the nitride layer of a gate stack to seep into adjacent photoresist layers and adversely affect the composition of the photoresist.
Claims29
A method of patterning and etching a semiconductor surface, the method comprising:
- forming an anti-reflective barrier on the semiconductor surface that has a first component tuned to absorb reflected light from the semiconductor surface in an unannealed state and a second component tuned to absorb reflected light from the semiconductor surface in an annealed state;
- positioning a first photoresist layer on the anti-reflective barrier;
- patterning and etching the first photoresist layer wherein the first component of the anti-reflective barrier inhibit light from being reflected from the semiconductor surface into the first photoresist layer during patterning and etching of the first photoresist layer;
- annealing the semiconductor surface following the patterning and etching of the first photoresist layer wherein the annealing step improves the ability of the second component of the anti-reflective barrier to inhibit reflected light to pass therethrough;
- depositing a second photoresist layer on the anti-reflective barrier;
- patterning and etching the second photoresist layer wherein the second component of the anti-reflection barrier inhibits light from being reflected from the semiconductor surface into the second photoresist layer during patterning and etching of the second photoresist layer.
A method of inhibiting light from reflecting off of an exposed surface of a semiconductor device during patterning and etching, the method comprising:
- positioning a first barrier layer on the exposed surface semiconductor device wherein the first barrier layer is configured to inhibit light reflecting from the exposed surface of the semiconductor device from traveling therethrough;
- positioning a second barrier layer on the first barrier layer wherein the second barrier layer is configured to inhibit light reflecting from the exposed surface of the semiconductor device from traveling therethrough before annealing;
- positioning a first photoresist layer on the second barrier layer;
- patterning and etching the first photoresist layer wherein the second barrier layer decreases the amount of reflected light reflecting from the exposed surface from entering the first photoresist layer during patterning and etching of the first photoresist layer;
- transforming the first barrier layer by annealing the semiconductor device so as to improve the ability of the first barrier layer to prevent light from being reflected from the exposed surface of the semiconductor device into a subsequently deposited photoresist layer during patterning and etching of the subsequently deposited photoresist layer.
A method of forming an anti-reflective barrier layer on a semiconductive device, the method comprising:
- forming a DARC layer that functions as an anti-reflective coating in an annealed state on a first surface of the device wherein the DARC layer substantially conforms to the topography of the first surface and has a substantially flat upper surface;
- forming a BARC layer that functions as an anti-reflective coating in an unannealed state on the upper surface of the DARC layer.
A method of forming a FLASH memory circuit, the method comprising:
- forming a gate stack on a substrate surface;
- forming a layer of DARC that functions as an anti-reflective coating in an annealed state onto an upper surface of the gate stack;
- forming a layer of BARC that functions as an anti-reflective coating in an unannealed state onto an upper surface of the DARC layer;
- forming a first layer of photoresist on the upper surface of the BARC layer;
- exposing the first layer of photoresist in a first print and etch operation;
- removing the layer of BARC from the upper surface of the DARC layer;
- annealing the gate stack;
- forming a second layer of photoresist on the upper surface of the DARC layer;
- exposing the second layer of photoresist in a second print and etch operation.
Dependencies are inferred from the claim text.