High speed packet switching controller for telephone switching system

Abstract

This invention relates to a high speed packet switching controller in a telephone switching system which can suitably be applied to a packet controller having large capacity using a neural network chip and maximize the system performance by the optimized switching operation. The high speed packet switching controller comprises a row address decoder for decoding a weight raw address which is inputted thereto, a column address decoder for decoding a weight column address which is inputted thereto, a matrix array for providing the neural network using address signals provided from the row address decoder and column address decoder and outputing varied voltage in accordance with an external weight value, a neural network for producing a final crossbar switching control signal, an external input/output bus for transmitting an output signal of the neural network, and an internal neural data bus for transmitting the address signal output from the row address decoder and column address decoder to the matrix array.

Dependencies are inferred from the claim text.