Variable offset amplifier circuit
AssigneeIntel Corporation
InventorBryan K. Casper
Life of this patent
Estimating the term…
Abstract
First and second differential transistor pairs, where each is intentionally unbalanced, are provided. Each pair has first and second output nodes. The first output node of the first pair is coupled to the second output node of the second pair. The second output node of the first pair is coupled to the first output node of the second pair. First and second variable current generators are coupled to control respective tail currents of the first and second differential pairs. Applications of the amplifier circuit include sense amplifiers and comparators.
Claims16
An amplifier circuit comprising:
- first and second differential transistor pairs each being intentionally unbalanced, each pair having first and second output nodes, the first output node of the first pair being coupled to the second output node of the second pair, the second output node of the first pair being coupled to the first output node of the second pair;
- and
- first and second variable current generators coupled to control respective tail currents of the first and second differential pairs.
A computer-implemented method for designing an amplifier circuit, comprising:
- creating a representation of first and second differential transistor pairs each being intentionally unbalanced, each pair having first and second output nodes, the first output node of the first pair being coupled to the second output node of the second pair, the second output node of the first pair being coupled to the first output node of the second pair;
- and
- creating a representation of first and second variable current generators that are coupled to control respective tail currents of the first and second differential pairs.
An amplifier circuit comprising:
- first and second differential transistor pairs, each pair having first and second output nodes, wherein for each differential transistor pair the first output node is coupled to be driven by a larger transistor of the pair and the second output node is coupled to be driven by a smaller transistor of the pair, the first output node of the first pair being coupled to the second output node of the second pair, the second output node of the first pair being coupled to the first output node of the second pair;
- and
- first and second variable current generators coupled to control respective tail currents of the first and second differential pairs.
Dependencies are inferred from the claim text.