Method and apparatus for asynchronously controlling state information within a circuit

A method for asynchronously controlling state information within a circuit, comprising:

• monitoring a voltage on a first conductor that indicates a state of the circuit;
• monitoring a condition input that indicates a condition;
• driving the first conductor to a first voltage level to indicate a first state based upon the condition indicated by the condition input and the state indicated by the voltage on the first conductor;
• driving the first conductor to a second voltage level to indicate a second state;
• monitoring a voltage on a second conductor that indicates a second state of the circuit;
• and
• asynchronously driving the second conductor to a first voltage level to indicate a first state based upon the state indicated by the voltage on the first conductor without waiting for a system clock signal to change state.

An apparatus for controlling asynchronous data transfers within a circuit, comprising:

• a first conductor that carries a voltage indicating a state of the circuit;
• a delay element, with an input coupled to the first conductor;
• a first N-type transistor, including a source coupled to ground and a gate coupled to a first signal line indicating a state condition;
• and
• a second N-type transistor, including a source coupled to a drain of the first N-type transistor, a gate coupled to an output of the delay element and a drain coupled to the first conductor;
• wherein if the first conductor and the first signal line both assume a high voltage level, the first conductor is driven to ground through a conducting path through the first N-type transistor and the second N-type transistor, and wherein the second N-type transistor shuts off after the gate of the second N-type transistor is driven to ground through the delay element.

An apparatus for controlling asynchronous data transfers within a circuit, comprising;

• a first conductor that carries a voltage indicating a state of the circuit;
• a first inverter with an input coupled to the first conductor;
• a first N-type transistor, including a source coupled to ground and a gate coupled to an output of the first inverter;
• a second N-type transistor, including a source coupled to a drain of the first N-type transistor, and a gate coupled to a first signal line indicating a state condition;
• and
• a first P-type transistor, including a source coupled to a high voltage and a drain coupled to a drain of the second N-type transistor;
• a delay element, including an input coupled to the drain of the first P-type transistor and an output coupled to a gate of the first P-type transistor;
• and
• a second P-type transistor with a source coupled to the high voltage, a gate coupled to the drain of the first P-type transistor, and a drain coupled to the first conductor;
• wherein if the first conductor assumes a low voltage level and the first signal line assumes a high voltage level, the first conductor is driven to the high voltage by the second P-type transistor, and wherein the second P-type transistor shuts off after the gate of the first P-type transistor is driven to the high voltage through the delay element.