Method of fabricating power rectifier device
AssigneeAPD Semiconductor, Inc.
InventorsPaul Chang, Vladimir Rodov, Geeng-Chuan Chern, Charles Lin, Ching-Lang Chiang
Life of this patent
Estimating the term…
Abstract
A vertical semiconductor rectifier device includes a semiconductor substrate of first conductivity type and having a plurality of gates insulatively formed on a first major surface and a plurality of source/drain regions of the first conductivity type formed in surface regions of second conductivity type in the first major surface adjacent to the gates. A plurality of channels of the second conductivity type each abuts a source/drain region and extends under a gate.
Claims20
A method of fabricating a semiconductor rectifier device comprising the steps of;
- a) providing a semiconductor substrate of a first conductivity type and having opposing major surfaces,
- b) forming a first silicon oxide layer on a first major surface,
- e) forming a first doped polysilicon layer on the first silicon oxide layer,
- d) forming pedestals of silicon oxide on the first polysilicon layer as a dopant implant mask,
- e) implanting first ions of a second conductive type in the substrate using the pedestals as a mask,
- f) forming sidewall spacers on the pedestals,
- g) implanting second ions of the second conductive type deeper into the substrate than the first ions using the pedestals with sidewalls as a mask,
- h) removing the first polysilicon layer and the first silicon oxide layer exposed between pedestals and sidewall spacers to define gates under the pedestals and sidewall spacers,
- i) implanting third ions of the first conducting type into the substrate and shallower than the first ions using the pedestals with sidewalls as a mask,
- j) annealing the implanted ions to form doped regions,
- k) removing the pedestals and sidewall spacers, and
- l) forming conductive metal layers on the first major surface and on the second major surface.
A method of fabricating a semiconductor rectifier device comprising the steps of:
- a) providing a semiconductor substrate of a first conductivity type and having opposing major surfaces,
- b) forming a first silicon oxide layer on a first major surface,
- c) forming a silicon nitride layer on the first silicon oxide layer,
- d) forming pedestals of silicon oxide on the first silicon nitride layer as a dopant implant mask,
- e) implanting first ions of a second conductive type in the substrate using the pedestals as a mask,
- f) forming sidewall spacers on the pedestals,
- g) implanting second ions of the second conductive type deeper into the substrate than the first ions using the pedestals with sidewalls as a mask,
- h) removing the first silicon nitride layer and first silicon oxide layer between the pedestals and sidewall spacers, thereby forming gate oxide under the pedestals and sidewall spacers,
- i) implanting third ions of the first conductivity type into the substrate and shallower than the first ions using the pedestals with sidewalls as a mask,
- j) annealing the implanted ions to form doped regions,
- k) removing the pedestals and sidewall spacers,
- l) removing silicon nitride covered by the pedestals leaving gate oxide, and
- m) forming conductive metal layers on the first major surface and on the second major surface.
Dependencies are inferred from the claim text.