Three-dimensional memory array and method of fabrication
AssigneeMatrix Semiconductor, Inc.
InventorsN. Johan Knall, Mark Johnson
Life of this patent
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Abstract
A multi-level memory array is described employing rail-stacks. The rail-stacks include a conductor and semiconductor layers. The rail-stacks are generally the diode is located in one rail-stack and the other half in the other rail-stack.
Claims22
A method for fabricating a multi-level memory array comprising the steps of:
- depositing a metal layer;
- forming at least one layer of silicon on the metal layer where the silicon is doped with a first conductivity type dopant;
- masking and etching the silicon and metal layers to define a plurality of parallel, spaced-apart rail-stacks;
- filling the space between the rail-stacks with a dielectric material;
- planarizing the silicon layer and the dielectric material to form a planarized surface, and
- forming a layer of material for an antifuse on the planarized surface.
A method for fabricating a multi-level memory array comprising the steps of:
- forming a metal layer;
- forming a first silicon layer heavily doped with a first conductivity type dopant on the metal layer;
- depositing a second silicon layer on the first silicon layer, the second silicon layer being more lightly doped than the first layer with the first conductivity type dopant;
- forming a layer of an antifuse material on the second silicon layer;
- depositing a third silicon layer on the layer of antifuse material heavily doped with a second conductivity type dopant;
- defining spaced-apart rail-stacks from the conductive layer, first and second silicon layers, the layer of antifuse material and third silicon layer;
- filling space between the rail-stacks with a dielectric, and
- planarizing the upper surface of the dielectric fill and the third silicon layer.
A method for fabricating a multi-level memory array comprising the steps of:
- forming a conductor layer;
- forming a first silicon layer doped with a first conductivity type dopant on the conductive layer;
- forming a second silicon layer on the first silicon layer, the second silicon layer being more lightly doped than the first layer with the first conductivity type dopant;
- forming a layer of an antifuse material on the second silicon layer;
- forming a third silicon layer on the layer of antifuse material doped with a second conductivity type dopant;
- defining spaced-apart first rail-stacks from the conductive layer, the first and second silicon layers, the layer of antifuse material and the third silicon layer;
- filling between the first rail-stacks with a dielectric, and
- planarizing the upper surface of the dielectric fill and the third silicon layer.
The method of claim 10 including repeating the steps of claim 75 to form second rail-stacks disposed above the first rail-stacks perpendicular to the first rail-stacks.
A method for fabricating a multi-level memory array comprising the steps of:
- forming a first silicon layer lightly doped with a first conductivity type dopant;
- forming a second silicon layer more heavily doped than the first layer with the first conductivity type dopant;
- depositing a conductive layer on the second silicon layer;
- depositing a third silicon layer heavily doped with a second conductivity type dopant;
- etching the first, second and third silicon layers and conductive layers to define a plurality of parallel, spaced-apart rail-stacks;
- filling the space between the rail-stacks with a dielectric material;
- planarizing the third silicon layer and the dielectric filling material, and
- depositing a layer of an antifuse material on the planarized surface.
Dependencies are inferred from the claim text.