Integrated system management memory for system management interrupt handler independent of BIOS and operating system
AssigneeIntel Corporation
InventorAndrew W. Martwick
Life of this patent
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Abstract
A memory controller with an integrated system management memory region is disclosed. The memory controller receives an SMI acknowledge signal from a processor. The processor then delivers a system management memory address to the memory controller. Instead of fetching SMI handler instructions from the address indicated by the processor, the memory controller instead fetches SMI handler instructions from its integrated system management memory region. At the end of the integrated system management memory's SMI handler, the processor is instructed to fetch instructions from the address originally specified by the processor. In this manner, a BIOS SMI routine may be executed after the integrated SMI routine is executed.
Claims19
An apparatus, comprising:
- an integrated system management memory region;
- and
- a system management interrupt address decode unit to fetch instructions from the integrated system management memory region in response to a system management interrupt acknowledge signal asserted by a processor, the system management interrupt decode unit to fetch instructions from the integrated system management memory region regardless of a system management interrupt address received from the processor.
A method, comprising:
- receiving a system management interrupt acknowledge signal from a processor;
- and
- fetching a plurality of system management interrupt handler instructions from an integrated system management memory in a memory controller regardless of a system management memory address indicated by the processor in responce to the system management interrupt acknowledge signal.
A system, comprising:
- a processor;
- a system main memory;
- and
- a memory controller coupled between the processor and the system main memory, the memory controller including
- an integrated system management memory region, and
- a system management interrupt address decode unit to fetch instructions from the integrated system management memory region in response to a system management interrupt acknowledge signal asserted by the processor, the system management interrupt decode unit to fetch instructions from the integrated system management memory region regardless of a system management interrupt address received from the processor.
Dependencies are inferred from the claim text.