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US 6,418,150 B1Granted
Method and apparatus for calibrating an IEEE-1394 cycle master
AssigneeApple Computer, Inc.
InventorErik P. Staats
Life of this patent
Estimating the term…
Abstract
A cycle master in a digital network having a bus architecture that complies with the IEEE-1394 Standard for a High Performance Serial Bus is calibrated by first computing a clock offset representing a difference between a first time synchronized to each of a plurality of packet arrival events and a second time synchronized to periodic ones of said plurality of packet arrival events; and then adjusting a frame rate of said packet arrival events to compensate for said clock offset.
Claims16
A method of calibrating a cycle master in a digital network, comprising the steps of:
- computing a clock offset representing a difference between a first time synchronized to each of a plurality of packet arrival events and a second time synchronized to periodic ones of said plurality of packet arrival events;
- and
- adjusting a frame rate of said packet arrival events to compensate for said clock offset.
A method comprising:
- measuring an accuracy of a cycle timer in a digital network by measuring a cycle clock offset between a cycle clock of the cycle timer and a cycle clock of a host adapter in the network;
- and
- adjusting a frame rate of data transmitted within the digital network according to the accuracy of the cycle timer.
A system comprising:
- means for synchronizing a first timer to each of a plurality of packet arrival events;
- means for synchronizing a second timer not to each one but to every K of said plurality of packet arrival events, where K is a positive integer greater than one;
- means for computing an offset between the first timer and the second timer;
- and
- means for adjusting a frame rate of said packet arrival events to compensate for said offset.
2 more elements
A system comprising:
- a transmitting device having a first timer;
- a receiving device having a second timer and a third timer;
- a point to point bus to be used by the transmitting and receiving devices to communicate with each other,
- the transmitting device to transmit a plurality of packets into the point to point bus, each packet having a time stamp from the first timer,
- the receiving device to receive each of the plurality of packets and synchronize (1) a second timer in accordance with the time stamp in each of the plurality of packets, and (2) a third timer in accordance with the time stamp that is not in each one but in every K of the plurality of packets, where K is a positive integer greater than one,
- the receiving device is to compute a difference between the second timer and the third timer, and then instruct the transmitting device to adjust its packet transmission rate to compensate for the difference.
3 more elements
Dependencies are inferred from the claim text.