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US 6,417,714 B1Granted
Method and apparatus for obtaining linear code-delay response from area-efficient delay cells
AssigneeInter Corporation
InventorsAhmed Biyabani, Krishnamurthy Soumyanath
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Abstract
An area-efficient delay cell utilizes transistor stacks to control positive feedback responsive to a counter code, thereby controlling the hysteresis and overall signal delay of the cell. The code-delay response of the cell can be modified by freezing the counter code at a convenient value. Linear superposition of the responses of one modified cell connected in series with one unmodified cell provides a more linear overall response and reduces jitter when used in a delay locked loop.
Claims32
A delay cell comprising:
- an inverter having an input terminal and an output terminal;
- and
- feedback circuitry coupled between the input terminal and the output terminal, wherein the feedback circuitry is constructed to control the amount of feedback responsive to a code;
- wherein the feedback circuitry comprises a first leg arranged to control a first current path between the input terminal and a first power supply terminal responsive to the code and an output signal from the inverter, and a second leg arranged to control a second current path between the input terminal and a second power supply terminal responsive to the code and the output signal from the inverter.
1 more element
A delay cell comprising:
- an inverter having an input terminal and an output terminal;
- and
- feedback circuitry coupled between the input terminal and the output terminal, wherein the feedback circuitry is constructed to control the amount of feedback responsive to a code;
- wherein the feedback circuitry comprises a delay stack coupled between the input terminal and the output terminal.
1 more element
A delay cell comprising:
- an inverter having an input terminal and an output terminal;
- and
- feedback circuitry coupled between the input terminal and the output terminal, wherein the feedback circuitry is constructed to control the amount of feedback responsive to a code;
- wherein the feedback circuitry comprises a delay stack coupled between the input terminal and the output terminal;
- and
- wherein:
- the delay stack comprises first and second transistors having channels coupled in series between the input terminal and a first power supply terminal;
- the first transistor has a gate coupled to the output terminal;
- the code is represented by a first code signal;
- and
- the second transistor has a gate for receiving the first code signal.
8 more elements
A delay cell comprising:
- an inverter having an input terminal and an output terminal;
- and
- feedback circuitry coupled between the input terminal and the output terminal, wherein the feedback circuitry is constructed to control the amount of feedback responsive to a code;
- wherein the feedback circuitry comprises a delay stack coupled between the input terminal and the output terminal;
- wherein the feedback circuitry further comprises a second delay stack coupled between the input terminal and the output terminal;
- and
- wherein the first and second delay stacks are binary weighted.
4 more elements
A delay cell comprising:
- an inverter having an input terminal and an output terminal;
- and
- feedback circuitry coupled between the input terminal and the output terminal, wherein the feedback circuitry is constructed to control the amount of feedback responsive to a code;
- wherein the feedback circuitry comprises a delay stack coupled between the input terminal and the output terminal;
- wherein the feedback circuitry further comprises a second delay stack coupled between the input terminal and the output terminal;
- and
- wherein the second delay stack is a composite delay stack comprising two delay stacks arranged in parallel.
4 more elements
A delay cell comprising:
- an inverter having an input terminal and an output terminal;
- and
- feedback circuitry coupled between the input terminal and the output terminal, wherein the feedback circuitry is constructed to control the amount of feedback responsive to a code;
- wherein the feedback circuitry comprises a delay stack coupled between the input terminal and the output terminal;
- wherein the feedback circuitry further comprises a second delay stack coupled between the input terminal and the output terminal;
- and
- wherein:
- the digital code comprises a first code signal and a second code signal;
- the first delay stack is arranged to operate responsive to the first code signal;
- and
- the second delay stack is arranged to operate responsive to the second code signal.
8 more elements
A delay locked loop comprising:
- a delay block for generating an output clock signal responsive to an input clock signal and a code;
- a phase detector coupled to the delay block for generating a control signal responsive to the input clock signal and the output clock signal;
- and
- a counter coupled between the phase detector and the delay block for generating the code responsive to the control signal;
- wherein the delay block comprises a delay cell comprising:
- an inverter having an input terminal and an output terminal;
- and
- feedback circuitry coupled between the input terminal and the output terminal, wherein the feedback circuitry is constructed to control the amount of feedback responsive to the code.
5 more elements
A delay locked loop comprising:
- a delay block for generating an output clock signal responsive to an input clock signal and a code;
- a phase detector coupled to the delay block for generating a control signal responsive to the input clock signal and the output clock signal;
- and
- a counter coupled between the phase detector and the delay block for generating the code responsive to the control signal;
- wherein the delay block comprises a delay cell comprising:
- an inverter having an input terminal and an output terminal;
- and
- feedback circuitry coupled between the input terminal and the output terminal, wherein the feedback circuitry is constructed to control the amount of feedback responsive to the code;
- wherein the delay block further comprises a second delay cell coupled to the first delay cell in a cascade arrangement, and wherein the second delay cell comprises:
- a second inverter having an input terminal and an output terminal;
- and
- second feedback circuitry coupled between the input terminal and the output terminal of the second inverter, wherein the second feedback circuitry is constructed to control the amount of feedback to the second inverter responsive to the code;
- and
- wherein:
- the code is represented by a first, second, third and fourth code signals;
- the first feedback circuitry comprises:
- a first delay stack coupled between the input and output terminals of the first inverter, and coupled to receive the first code signal, and
- a second delay stack coupled between the input and output terminals of the first inverter, and coupled to receive the second code signal;
- and
- the second feedback circuitry comprises:
- a third delay stack coupled between the input and output terminals of the second inverter, and coupled to receive the third code signal, and
- a fourth delay stack coupled between the input and output terminals of the second inverter, and coupled to receive the fourth code signal.
19 more elements
A delay block comprising:
- a plurality of delay cells coupled in a cascade arrangement for generating an output clock signal responsive to an input clock signal and a code;
- logic circuitry coupled to the plurality of delay cells for transmitting a portion of the code to each of the delay cells, wherein the logic circuitry is constructed so as to modify one of the portions of the code as the code changes.
A delay locked loop comprising:
- a delay block for generating an output clock signal responsive to an input clock signal and a code;
- a phase detector coupled to the delay block for generating a control signal responsive to the input clock signal and the output clock signal;
- and
- a counter coupled between the phase detector and the delay block for generating the code responsive to the control signal;
- wherein the delay block comprises:
- a plurality of delay cells coupled in a cascade arrangement for generating the output clock signal responsive to the input clock signal and the code;
- logic circuitry coupled to the plurality of delay cells and the counter for transmitting a portion of the code to each of the delay cells, wherein the logic circuitry is constructed so as to modify one of the portions of the code as the code changes.
4 more elements
A semiconductor die having a delay cell fabricated thereon, the delay cell comprising:
- an inverter having an input terminal and an output terminal;
- and
- feedback circuitry coupled between the input terminal and the output terminal, wherein the feedback circuitry is constructed to control the amount of feedback responsive to a code;
- wherein the feedback circuitry comprises a first leg arranged to control a first current path between the input terminal and a first power supply terminal responsive to the code and an output signal from the inverter, and a second leg arranged to control a second current path.
1 more element
A semiconductor die having a delay cell fabricated thereon, the delay cell comprising:
- an inverter having an input terminal and an output terminal;
- and
- feedback circuitry coupled between the input terminal and the output terminal, wherein the feedback circuitry is constructed to control the amount of feedback responsive to a code;
- wherein the feedback circuitry comprises a delay stack coupled between the input terminal and the output terminal;
- and
- wherein:
- the delay stack comprises first and second transistors having channels coupled in series between the input terminal and a first power supply terminal;
- the first transistor has a gate coupled to the output terminal;
- the code is represented by a first code signal;
- and
- the second transistor has a gate for receiving the first code signal.
8 more elements
A semiconductor die having a delay block fabricated thereon, the delay block comprising:
- a plurality of delay cells coupled in a cascade arrangement for generating an output clock signal responsive to an input clock signal and a code;
- logic circuitry coupled to the plurality of delay cells for transmitting a portion of the code to each of the delay cells, wherein the logic circuitry is constructed so as to modify one of the portions of the code as the code changes.
A delay cell comprising:
- an inverter having an input terminal and an output terminal;
- and
- feedback circuitry coupled between the input terminal and the output terminal, wherein the feedback circuitry is constructed to control the amount of feedback responsive to a code;
- wherein the feedback circuitry comprises a first leg having a first resistance and a second leg having a second resistance;
- and
- wherein the first and second resistances are asymmetric.
3 more elements
Dependencies are inferred from the claim text.