Bridging device for mapping/demapping ethernet packet data directly onto and from a sonet network
AssigneeOSS Corporation
InventorsMilind M Kulkarni, Mahabala Shetty, Suresh K. Pillai
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AssigneeOSS Corporation
InventorsMilind M Kulkarni, Mahabala Shetty, Suresh K. Pillai
Estimating the term…
A bridging device for mapping and demapping Ethernet data packets onto a SONET network includes an Ethernet controller chip set which receives packet data, a SONET framer for a SONET interface, a UTOPIA interface for the SONET framer, and an FPGA (or ASIC) which bridges the UTOPIA interface and a system bus interface of the Ethernet controller. The FPGA is preferably implemented in VHDL software code as several modules: an Ethernet controller interface module, a chunk memory module, a UTOPIA interface module, a microprocessor interface module, and a UTOPIA OUT module. In a transmit mode, the Ethernet controller interface module interfaces with the data and control signals from a thirty-two bit data bus of the Ethernet controller chip set and writes the data to chunk memory implemented in the FPGA. The chunk memory module implements the chunk memory to a programmable size. The UTOPIA interface module implements an interface with data and control bus signals of Fr-UTOPIA and reads data sixteen bits at a time from chunk memory and writes the data to the Fr-UTOPIA interface bus. The microprocessor interface module implements the control and status registers. The UTOPIA OUT module implements address and data bus drivers and control signals of the Fr-UTOPIA data bus. A top level module instantiates the modules with proper signals. The bridging device is also adapted for a receive mode in which an FPGA operates substantially in reverse.
A bridging device for mapping and demapping data from Ethernet channel to and from a SONET network, said bridging device comprising:
An FPGA or an ASIC for mapping data of a data frame between an Ethernet controller chip set coupled to an Ethernet channel and a SONET framer coupled to a SONET network, said FPGA or ASIC comprising:
An FPGA or an ASIC for mapping data of a data frame from a SONET framer coupled to a SONET network to an Ethernet controller chip set coupled to an Ethernet channel, said FPGA or ASIC comprising:
A method of mapping Ethernet data packets from a Ethernet channel to a SONET network, said method comprising:
A method of mapping SONET data from a SONET framer onto an Ethernet channel, said method comprising:
Dependencies are inferred from the claim text.