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US 6,414,873 B1Granted
nvSRAM with multiple non-volatile memory cells for each SRAM memory cell
AssigneeSimtek
InventorChristian E. Herdt
Life of this patent
Estimating the term…
Abstract
The invention relates to a non-volatile, static random access memory (nvSRAM) in which there are at least two, non-volatile memory cells associated with each SRAM memory cell. The non-volatile memory cells are capable of being programmed with whatever bit of information is present in the SRAM at two different times. In one embodiment, the non-volatile memory cells are capable of being randomly programmed, i.e., programmed in any order. Further, the bits of data programmed into the non-volatile memory cells can be recalled in any order, i.e., randomly recalled.
Claims19
A non-volatile, static random access memory (nvSRAM) with the ability to store multiple bits of data for each static random access memory cell comprising:
- a static random access memory that is capable of receiving a bit of data from an exterior environment, retaining a bit of data, and transmitting a bit of data to the exterior environment;
- wherein a bit of data stored in said static random access memory can be lost if power is removed from said static random access memory;
- a non-volatile memory, operatively connected to said static random access memory, that includes a first non-volatile memory cell capable of being programmed with a differentially represented bit of data received from said static random access memory and a second nonvolatile memory cell that is also capable of being programmed with a differentially represented bit of data received from said static random access memory;
- wherein said first non-volatile memory cell is in series with said second non-volatile memory cell and located between said second non-volatile memory cell and said static random access memory;
- and
- a controller, operatively connected to said static random access memory and said nonvolatile memory, that is capable of causing said non-volatile memory to be programmed with a first differentially represented bit of data stored in said static random access memory at a first time and a second differentially represented bit of data stored in said static random access memory at a second time that is different than said first time.
3 more elements
A non-volatile, static random access memory (nvSRAM) with the ability to store multiple bits of data for each static random access memory cell comprising:
- a static random access memory that is capable of receiving a bit of data from an exterior environment, retaining a bit of data, and transmitting a bit of data to the exterior environment;
- wherein a bit of data stored in said static random access memory can be lost if power is removed from said static random access memory;
- a non-volatile memory, operatively connected to said static random access memory, that includes a first non-volatile memory cell capable of being a dfferentially represented bit of data received from said static random access memory, a second non-volatile memory cell that is also capable of being programmed with a differentially represented bit of data received from said static random access memory;
- a first switching device for selectively connecting and disconnecting said static random access memory and said non-volatile memory;
- a second switching device for selectively connecting and disconnecting said non-volatile memory and a power supply connection;
- wherein said first non-volatile memory cell is in series with said second non-volatile memory cell and located between said second non-volatile memory cell and said static random access memory;
- a controller, operatively connected to said static random access memory and said non-volatile memory, that is capable of causing said non-volatile memory to be programmed with a first differentially represented bit of data stored in said static random access memory at a first time and a second differentially represented bit of data stored in said static random access memory at a second time that is different than said first time.
4 more elements
A non-volatile, static random access memory (nvSRAM) with the ability to store multiple bits of data for each static random access memory cell comprising:
- a static random access memory that is capable of receiving a bit of data from an exterior environment, retaining a bit of data, and transmitting a bit of data to the exterior environment;
- wherein a bit of data stored in said static random access memory can be lost if power is removed from said static random access memory;
- a non-volatile memory, operatively connected to said static random access memory, that includes a first non-volatile memory cell capable of being programmed with a differentially represented bit of data received from said static random access memory and a second non-volatile memory cell that is also capable of being programmed with a differentially represented bit of data received from said static random access memory;
- an isolation device, located between said static random access memory and said non-volatile memory, to prevent said static random access memory from experiencing a voltage outside the normal voltage range for read and write operations to said static random access memory during a programming of said non-volatile memory;
- a controller, operatively connected to said static random access memory and said non-volatile memory, that is capable of causing said non-volatile memory to be programmed with a first differentially represented bit of data stored in said static random access memory at a first time and a second differentially represented bit of data stored in said static random access memory at a second time that is different than said first time.
2 more elements
Dependencies are inferred from the claim text.