Equal delay current-mode logic circuit
AssigneeApplied Micro Circuits Corporation
InventorBrian Lee Abernathy
Life of this patent
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Abstract
A differential signal current-mode logic (CML) circuit is provided which provides an equal delay output. Convention differential logic CML circuits have upper stage and lower stage transistors pairs. Input signals that are provided to the lower stage are necessarily delayed with respect to inputs provided to the upper stage. The present invention provides parallel upper stage sections so that each input signal is translated to the output through the same number of transistors. Thus, the delay associated with each input signal is made equal. Specific examples of exclusive OR, OR, and AND circuits are provided.
Claims23
In an integrated circuit, a current-mode logic (CML) circuit for supplying a differential output signal with equal delays, the circuit comprising:
- a first differential cascode section having an upper transistor stage to accept a first differential input signal and a lower transistor stage to accept an offset second differential input signal;
- a second differential cascode section having an upper transistor stage to accept a second differential input signal and a lower transistor stage to accept an offset first differential input signal;
- and
- a first diode having an anode to accept the first polarity of the first differential input signal and a cathode to supply the first polarity of the offset first differential input signal;
- a second diode having an anode to accept the second polarity of the first differential input signal and a cathode to supply the second polarity of the offset first differential input signal;
- a third diode having an anode to accept the first polarity of the second differential input signal and a cathode to supply the first polarity of the offset second differential input signal;
- and
- a fourth diode having an anode to accept the second polarity of the second differential input signal and a cathode to supply the second polarity of the offset second differential input signal;
- wherein the first and second cascode sections are connected to supply a differential output signal having equal delays in response to the first differential input signal, the second differential input signal, the first offset differential input signal, and the second offset differential signal.
In an integrated circuit current-mode logic circuit, a method for supplying a differential output signal with equal delays, the method comprising:
- accepting a first differential signal, wherein a first polarity of the first differential signal is accepted at an anode of a first diode, and a second polarity of the first differential signal is accepted at a anode of a second diode;
- accepting an offset first differential signal with a voltage level offset from the first differential signal, wherein a first polarity of the offset first differential signal is supplied by a cathode of the first diode, and a second polarity of the offset first differential signal is supplied by a cathode of the second diode;
- accepting a second differential signal, wherein a first polarity of the second differential signal is accepted at an anode of a third diode, and a second polarity of the second differential signal is accepted at an anode of a fourth diode,
- accepting an offset second differential signal with a voltage level offset from the second differential signal, wherein a first polarity of the offset second differential signal is supplied by a cathode of the third diode, and a second polarity of the offset second differently signal is supplied by a cathode of the fourth diode;
- performing a first logical operation using the first differential signal and the offset second differential signal;
- supplying a first operation differential signal product having a first delay associated with the first differential signal and a second delay, greater than the first delay, associated with the offset second differential signal;
- performing the first logical operation using the second differential signal and the offset first differential signal;
- supplying a first operation differential signal product having a first delay associated with the second differential signal and a second delay, greater than the first delay, associated with the offset first differential signal;
- and
- combining the supplied first operation differential signal products to supply a combined first operation differential signal product having a first delay.
Dependencies are inferred from the claim text.